Datasheet
ADS1274
ADS1278
SBAS367F –JUNE 2007–REVISED FEBRUARY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
All specifications at T
A
= –40°C to +105°C, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, f
CLK
= 27MHz, VREFP = 2.5V,
VREFN = 0V, and all channels active, unless otherwise noted.
ADS1274, ADS1278
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
Crosstalk f = 1kHz, –0.5dBFS
(5)
–107 dB
High-Speed mode 101 106 dB
V
REF
= 2.5V 103 110 dB
High-Resolution mode
Signal-to-noise ratio (SNR)
(6)
V
REF
= 3V 111 dB
(unweighted)
Low-Power mode 101 106 dB
Low-Speed mode 101 107 dB
Total harmonic distortion (THD)
(7)
V
IN
= 1kHz, –0.5dBFS –108 –96 dB
Spurious-free dynamic range 109 dB
Passband ripple ±0.005 dB
Passband 0.453 f
DATA
Hz
–3dB Bandwidth 0.49 f
DATA
Hz
High-Resolution mode 95 dB
Stop band attenuation
All other modes 100
High-Resolution mode 0.547 f
DATA
127.453 f
DATA
Hz
Stop band
All other modes 0.547 f
DATA
63.453 f
DATA
Hz
High-Resolution mode 39/f
DATA
s
Group delay
All other modes 38/f
DATA
s
High-Resolution mode Complete settling 78/f
DATA
s
Settling time (latency)
All other modes Complete settling 76/f
DATA
s
VOLTAGE REFERENCE INPUTS
Negative reference input (VREFN) AGND – 0.1 AGND + 0.1 V
0.1 ≤ f
CLK
≤ 27MHz 0.5 2.5 3.1 V
Reference input voltage (V
REF
)
(8)
27 < f
CLK
≤ 32.768MHz 0.5 2.5 2.6 V
(V
REF
= VREFP – VREFN)
32.768MHz < f
CLK
≤ 37MHz 0.5 2.048 2.1 V
High-Speed mode 1.3 kΩ
High-Resolution mode 1.3 kΩ
ADS1274
Reference Input impedance
Low-Power mode 2.6 kΩ
Low-Speed mode 13 kΩ
High-Speed mode 0.65 kΩ
High-Resolution mode 0.65 kΩ
ADS1278
Reference Input impedance
Low-Power mode 1.3 kΩ
Low-Speed mode 6.5 kΩ
DIGITAL INPUT/OUTPUT (IOVDD = 1.8V to 3.6V)
V
IH
0.7 IOVDD IOVDD V
V
IL
DGND 0.3 IOVDD V
V
OH
I
OH
= 4mA 0.8 IOVDD IOVDD V
V
OL
I
OL
= 4mA DGND 0.2 IOVDD V
Input leakage 0 < V
IN DIGITAL
< IOVDD ±10 μA
High-Speed mode
(8)
0.1 37 MHz
Master clock rate (f
CLK
)
Other modes 0.1 27 MHz
(5) Worst-case channel crosstalk between one or more channels.
(6) Minimum SNR is ensured by the limit of the DC noise specification.
(7) THD includes the first nine harmonics of the input signal; Low-Speed mode includes the first five harmonics.
(8) f
CLK
= 37MHz max for High-Speed mode, and 27MHz max for all other modes. See Table 7 for V
REF
restrictions in High-Speed mode.
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