Datasheet

IN1(+)
AINP1
AINN1
IN4/8(+)
+3.3V
+1.8V
(6)
AINP4/8
AINN4/8
AVDD
DVDD
VREFP
VREFN
VCOM
TEST0
TEST1
DIN
AGND
DGND
IOVDD
CLK
DRDY/FSYNC
DVDD(I/O)
DR
FSR
DOUT1
SCLK
CVDD
(CORE)
DOUT2
DOUT3
DOUT4
SYNC
PWDN1 I/O
PWDN2
PWDN3
PWDN4
CLKDIV
FORMAT2
MODE1
FORMAT1
FORMAT0
10 Fm
(2)
+
10 Fm
(2)
10 Fm
+
0.1 Fm
(2)
0.1 Fm
(2)
REF5025
+5V
10 Fm
(2)
50W
+3.3V
(High-Speed,Frame-Sync,TDM,
andFixed-Positiondataselected.)
ADS1274/ADS1278 TMS320VC5509
200MHz
+1.6V
THS4521
(1)
2.2nF
(3)
2.2nF
(3)
(4)
OPA350
Buffered
VCOM
Output
100W
See
Note(5)
50W
U1
U2
CLKR
Q
Q
0
>
+3.3V
MODE0
IN1( )-
¼ ¼
IN4/8( )-
1 Fm
+5V
See
Note(6)
ADS1274
ADS1278
SBAS367F –JUNE 2007–REVISED FEBRUARY 2011 www.ti.com
(1) External Schottky clamp diodes or series resistors may be needed to prevent overvoltage on the inputs. Place the THS4521 drivers close
to the ADS1278 inputs.
(2) Indicates ceramic capacitors.
(3) Indicates COG ceramic capacitors.
(4) Optional. For pin test mode.
(5) U1: SN74LVC1G04; U2: SN74LVC2G74. These components re-clock the ADS1274/78 data output to interface to the TMS320VC5509.
(6) If CLK > 32.768MHz, use the REF5020 and DVDD = 2.1V.
Figure 88. ADS1274 Basic Connection Drawing
38 Submit Documentation Feedback © 2007–2011, Texas Instruments Incorporated
Product Folder Link(s): ADS1274 ADS1278