Datasheet
SCLK
DOUT
Modulator
ClockOutput
Modulator
DataOutput
(13nsmax)
OPA350
0.1 Fm
VCOM VDD/2)(A»
ADS1274/78
ADS1274
ADS1278
SBAS367F –JUNE 2007–REVISED FEBRUARY 2011
www.ti.com
Table 17. Test Mode Pin Map (TEST[1:0] = 11)
In modulator output mode, the frequency of the
modulator clock output (SCLK) depends on the mode
TEST MODE PIN MAP
selection of the ADS1274/78. Table 16 lists the
INPUT PINS OUTPUT PINS
modulator clock output frequency and DVDD current
PWDN1 DOUT1
versus device mode.
PWDN2 DOUT2
Figure 86 shows the timing relationship of the
PWDN3 DOUT3
modulator clock and data outputs.
PWDN4 DOUT4
The data output is a modulated 1s density data
PWDN5 DOUT5
stream. When V
IN
= +V
REF
, the 1s density is
PWDN6 DOUT6
approximately 80% and when V
IN
= –V
REF
, the 1s
PWDN7 DOUT7
density is approximately 20%.
PWDN8 DOUT8
MODE0 DIN
MODE1 SYNC
FORMAT0 CLKDIV
FORMAT1 FSYNC/DRDY
FORMAT2 SCLK
Figure 86. Modulator Output Timing
VCOM OUTPUT
The VCOM pin provides a voltage output equal to
AVDD/2. The intended use of this output is to set the
PIN TEST USING TEST[1:0] INPUTS
output common-mode level of the analog input
The test mode feature of the ADS1274 and ADS1278
drivers. The drive capability of the output is limited;
allows continuity testing of the digital I/O pins. In this
therefore, the output should only be used to drive
mode, the normal functions of the digital pins are
high-impedance nodes (> 1MΩ). In some cases, an
disabled and routed to each other as pairs through
external buffer may be necessary. A 0.1μF bypass
internal logic, as shown in Table 17. The pins in the
capacitor is recommended to reduce noise pickup.
left column drive the output pins in the right column.
Note: some of the digital input pins become outputs;
these outputs must be accommodated in the design.
The analog input, power supply, and ground pins all
remain connected as normal. The test mode is
engaged by setting the pins TEST [1:0] = 11. For
normal converter operation, set TEST[1:0] = 00. Do
not use '01' or '10'.
Figure 87. VCOM Output
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