Datasheet

CH1
DOUT1
( )ADS1274
SCLK
DRDY
(SPI)
FSYNC
(Frame-Sync)
1 2
24 2523 48 4947
72
73
71
96 9795
CH1
DOUT1
( )ADS1278
169
CH2
CH2
CH3
CH3
CH4
CH4 CH5
191
CH8 DIN
192 193 194 195
CH7
DIN
168167
ADS1274
ADS1278
www.ti.com SBAS367F –JUNE 2007– REVISED FEBRUARY 2011
DOUT
FRAME-SYNC SERIAL INTERFACE
The conversion data are shifted out on
Frame-Sync format is similar to the interface often
DOUT[4:1]/[8:1]. The MSB data become valid on
used on audio ADCs. It operates in slave
DOUT[4:1]/[8:1] after FSYNC goes high. The
fashion—the user must supply framing signal FSYNC
subsequent bits are shifted out with each falling edge
(similar to the left/right clock on stereo audio ADCs)
of SCLK. If daisy-chaining, the data shifted in using
and the serial clock SCLK (similar to the bit clock on
DIN appear on DOUT[4:1]/[8:1] after all channel data
audio ADCs). The data are output MSB first or
have been shifted out. When the device is configured
left-justified on the rising edge of FSYNC. When
for modulator output, DOUT becomes the modulator
using Frame-Sync format, the FSYNC and SCLK
data output (see the Modulator Output section).
inputs must be continuously running with the
relationships shown in the Frame-Sync Timing
DIN
Requirements.
This input is used when multiple ADS1274/78s are to
SCLK
be daisy-chained together. It can be used with either
SPI or Frame-Sync formats. Data are shifted in on
The serial clock (SCLK) features a Schmitt-triggered
the falling edge of SCLK. When using only one
input and shifts out data on DOUT on the falling
ADS1274/78, tie DIN low. See the Daisy-Chaining
edge. It also shifts in data on the falling edge on DIN
section for more information.
when this pin is being used for daisy-chaining. Even
though SCLK has hysteresis, it is recommended to
keep SCLK as clean as possible to prevent glitches DOUT MODES
from accidentally shifting the data. When using
For both SPI and Frame-Sync interface protocols, the
Frame-Sync format, SCLK must run continuously. If it
data are shifted out either through individual channel
is shut down, the data readback will be corrupted.
DOUT pins, in a parallel data format (Discrete mode),
The number of SCLKs within a frame period (FSYNC
or the data for all channels are shifted out, in a serial
clock) can be any power-of-2 ratio of CLK cycles (1,
format, through a common pin, DOUT1 (TDM mode).
1/2, 1/4, etc), as long as the number of cycles is
sufficient to shift the data output from all channels
TDM Mode
within one frame. When the device is configured for
modulator output, SCLK becomes the modulator
In TDM (time-division multiplexed) data output mode,
clock output (see the Modulator Output section).
the data for all channels are shifted out, in sequence,
on a single pin (DOUT1). As shown in Figure 77, the
DRDY/FSYNC (Frame-Sync Format)
data from channel 1 are shifted out first, followed by
channel 2 data, etc. After the data from the last
In Frame-Sync format, this pin is used as the FSYNC
channel are shifted out, the data from the DIN input
input. The frame-sync input (FSYNC) sets the frame
follow. The DIN is used to daisy-chain the data output
period, which must be the same as the data rate. The
from an additional ADS1274/78 or other compatible
required number of f
CLK
cycles to each FSYNC period
device. Note that when all channels of the
depends on the mode selection and the CLKDIV
ADS1274/78 are disabled, the interface is disabled,
input. Table 8 indicates the number of CLK cycles to
rendering the DIN input disabled as well. When one
each frame (f
CLK
/f
DATA
). If the FSYNC period is not
or more channels of the device are powered down,
the proper value, data readback will be corrupted.
the data format of the TDM mode can be fixed or
dynamic.
Figure 77. TDM Mode (All Channels Enabled)
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