Datasheet

DRDY
SCLK
1/f
DATA
1/f
CLK
ADS1274
ADS1278
SBAS367F –JUNE 2007–REVISED FEBRUARY 2011 www.ti.com
FORMAT[2:0] Even though the SCLK input has hysteresis, it is
recommended to keep SCLK as clean as possible to
Data can be read from the ADS1274/78 with two
prevent glitches from accidentally shifting the data.
interface protocols (SPI or Frame-Sync) and several
options of data formats (TDM/Discrete and SCLK may be run as fast as the CLK frequency.
Fixed/Dynamic data positions). The FORMAT[2:0] SCLK may be either in free-running or stop-clock
inputs are used to select among the options. Table 14 operation between conversions. Note that one f
CLK
is
lists the available options. See the DOUT Modes required after the falling edge of DRDY until the first
section for details of the DOUT Mode and Data rising edge of SCLK. For best performance, limit
Position. f
SCLK
/f
CLK
to ratios of 1, 1/2, 1/4, 1/8, etc. When the
device is configured for modulator output, SCLK
Table 14. Data Output Format becomes the modulator clock output (see the
Modulator Output section).
INTERFACE DOUT DATA
FORMAT[2:0] PROTOCOL MODE POSITION
DRDY/FSYNC (SPI Format)
000 SPI TDM Dynamic
In the SPI format, this pin functions as the DRDY
001 SPI TDM Fixed
output. It goes low when data are ready for retrieval
010 SPI Discrete —
and then returns high on the falling edge of the first
011 Frame-Sync TDM Dynamic
subsequent SCLK. If data are not retrieved (that is,
100 Frame-Sync TDM Fixed
SCLK is held low), DRDY pulses high just before the
101 Frame-Sync Discrete —
next conversion data are ready, as shown in
Figure 76. The new data are loaded within one CLK
110 Modulator Mode — —
cycle before DRDY goes low. All data must be shifted
out before this time to avoid being overwritten.
SERIAL INTERFACE PROTOCOLS
Data are retrieved from the ADS1274/78 using the
serial interface. Two protocols are available: SPI and
Frame-Sync. The same pins are used for both
interfaces: SCLK, DRDY/FSYNC, DOUT[4:1]
(DOUT[8:1] for ADS1278), and DIN. The
FORMAT[2:0] pins select the desired interface
Figure 76. DRDY Timing with No Readback
protocol.
SPI SERIAL INTERFACE
DOUT
The SPI-compatible format is a read-only interface.
The conversion data are output on DOUT[4:1]/[8:1].
Data ready for retrieval are indicated by the falling
The MSB data are valid on DOUT[4:1]/[8:1] after
DRDY output and are shifted out on the falling edge
DRDY goes low. Subsequent bits are shifted out with
of SCLK, MSB first. The interface can be
each falling edge of SCLK. If daisy-chaining, the data
daisy-chained using the DIN input when using
shifted in using DIN appear on DOUT after all
multiple devices. See the Daisy-Chaining section for
channel data have been shifted out. When the device
more information.
is configured for modulator output, DOUT[4:1]/[8:1]
becomes the modulator data output for each channel
NOTE: The SPI format is limited to a CLK input
(see the Modulator Output section).
frequency of 27MHz, maximum. For CLK input
operation above 27MHz (High-Speed mode only),
DIN
use Frame-Sync format.
This input is used when multiple ADS1274/78s are to
SCLK
be daisy-chained together. The DOUT1 pin of the first
device connects to the DIN pin of the next, etc. It can
The serial clock (SCLK) features a Schmitt-triggered
be used with either the SPI or Frame-Sync formats.
input and shifts out data on DOUT on the falling
Data are shifted in on the falling edge of SCLK. When
edge. It also shifts in data on the falling edge on DIN
using only one ADS1274/78, tie DIN low. See the
when this pin is being used for daisy-chaining. The
Daisy-Chaining section for more information.
device shifts data out on the falling edge and the user
normally shifts this data in on the rising edge.
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