Datasheet

CLK
DRDY/FSYNC
(1)
DOUT
(DiscreteDataOutputMode)
· · ·· · ·
PWDN
t
NDR
t
PWDN
P -UpDataostPower
DOUT1
(TDMMode,DynamicPosition)
NormalPosition
NormalPositionDataShiftsPosition
NormalPosition
NormalPositionDataRemainsinPosition
DOUT1
(TDMMode,FixedPosition)
ADS1274
ADS1278
www.ti.com SBAS367F –JUNE 2007– REVISED FEBRUARY 2011
POWER-DOWN (PWDN) 3. Detect for non-zero data in the powered-up
channel.
The channels of the ADS1274/78 can be
independently powered down by use of the PWDN After powering up one or more channels, the
inputs. To enter the power-down mode, hold the channels are synchronized to each other. It is not
respective PWDN pin low for at least two CLK cycles. necessary to use the SYNC pin to synchronize them.
To exit power-down, return the corresponding PWDN
When a channel is powered down in TDM data
pin high. Note that when all channels are powered
format, the data for that channel are either forced to
down, the ADS1274/78 enters a microwatt (μW)
zero (fixed-position TDM data mode) or replaced by
power state where all internal biasing is disabled. In
shifting the data from the next channel into the
this state, the TEST[1:0] input pins must be driven; all
vacated data position (dynamic-position TDM data
other input pins can float. The ADS1274/78 outputs
mode).
remain driven.
In Discrete data format, the data are always forced to
As shown in Figure 75 and Table 13, a maximum of
zero. When powering-up a channel in
130 conversion cycles must elapse for SPI interface,
dynamic-position TDM data format mode, the channel
and 129 conversion cycles must elapse for
data remain packed until the data are ready, at which
Frame-Sync, before reading data after exiting
time the data frame is expanded to include the
power-down. Data from channels already running are
just-powered channel data. See the Data Format
not affected. The user software can perform the
section for details.
required delay time in any of the following ways:
1. Count the number of data conversions after
taking the PWDN pin high.
2. Delay 129/f
DATA
or 130/f
DATA
after taking the
PWDN pins high, then read data.
(1) In SPI protocol, the timing occurs on the falling edge of DRDY/FSYNC. Powering down all channels forces DRDY/FSYNC high.
Figure 75. Power-Down Timing
Table 13. Power-Down Timing
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
PWDN
PWDN pulse width to enter Power-Down mode 2 CLK periods
t
NDR
Time for new data ready (SPI) 129 130 Conversions (1/f
DATA
)
t
NDR
Time for new data ready (Frame-Sync)
(1)
128 129 Conversions (1/f
DATA
)
(1) FSYNC clock running prior to the rising edge of PWDN. If PWDN is asynchronous to the FSYNC clock, t
NDR-FS
varies from 127 to 128
conversions. If PWDN is made synchronous to FSYNC, then t
NDR-FS
is stable.
© 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Link(s): ADS1274 ADS1278