Datasheet

ADS1274
ADS1278
SBAS367F –JUNE 2007–REVISED FEBRUARY 2011 www.ti.com
ESD diodes protect the reference inputs. To keep As with any high-speed data converter, a high-quality,
these diodes from turning on, make sure the voltages low-jitter clock is essential for optimum performance.
on the reference pins do not go below AGND by Crystal clock oscillators are the recommended clock
more than 0.4V, and likewise do not exceed AVDD by source. Make sure to avoid excess ringing on the
0.4V. If these conditions are possible, external clock input; keeping the clock trace as short as
Schottky clamp diodes or series resistors may be possible, and using a 50Ω series resistor placed
required to limit the input current to safe values (see close to the source end, often helps.
the Absolute Maximum Ratings table).
Table 8. Clock Input Options
A high-quality reference voltage with the appropriate
MODE MAX f
CLK
DATA RATE
drive strength is essential for achieving the best
SELECTION (MHz) CLKDIV f
CLK
/f
DATA
(SPS)
performance from the ADS1274. Noise and drift on
High-Speed 37 1 256 144,531
the reference degrade overall system performance.
High-Resolution 27 1 512 52,734
See the Application Information section for example
27 1 512
reference circuits.
Low-Power 52,734
13.5 0 256
CLOCK INPUT (CLK)
27 1 2,560
Low-Speed 10,547
5.4 0 512
The ADS1274/78 requires a clock input for operation.
The individual converters of the ADS1274/78 operate
from the same clock input. At the maximum data rate,
MODE SELECTION (MODE)
the clock input can be either 27MHz or 13.5MHz for
The ADS1274/78 supports four modes of operation:
Low-Power mode, or 27MHz or 5.4MHz for
High-Speed, High-Resolution, Low-Power, and
Low-Speed mode, determined by the setting of the
Low-Speed. The modes offer optimization of speed,
CLKDIV input. For High-Speed mode, the maximum
resolution, and power. Mode selection is determined
CLK input frequency is 37MHz. For High-Resolution
by the status of the digital input MODE[1:0] pins, as
mode, the maximum CLK input frequency is 27MHz.
shown in Table 9. The ADS1274/78 continually
In High-Speed mode, operating conditions are
monitors the status of the MODE pin during
restricted depending on the clock input frequency.
operation.
The limitations are summarized in Table 7.
Table 9. Mode Selection
Table 7. High-Speed Mode f
CLK
Conditions
MODE[1:0] MODE SELECTION MAX f
DATA
(1)
V
REF
00 High-Speed 144,531
f
CLK
(MHz) (V) DVDD (V) INTERFACE
01 High-Resolution 52,734
0.5 to
0.1 ≤ f
CLK
≤ 27 1.65 to 1.95 Frame-Sync or SPI
3.1
10 Low-Power 52,734
0.5 to
11 Low-Speed 10,547
27 < f
CLK
≤ 32.768 1.65 to 1.95 Frame-Sync
2.6
(1) f
CLK
= 27MHz max (37MHz max in High-Speed mode).
0.5 to
32.768 < f
CLK
≤ 37 2.0 to 2.2 Frame-Sync
2.1
When using the SPI protocol, DRDY is held high after
a mode change occurs until settled (or valid) data are
The selection of the external clock frequency (f
CLK
)
ready; see Figure 72 and Table 10.
does not affect the resolution of the ADS1274/78.
In Frame-Sync protocol, the DOUT pins are held low
Use of a slower f
CLK
can reduce the power
after a mode change occurs until settled data are
consumption of an external clock buffer. The output
ready; see Figure 72 and Table 10. Data can be read
data rate scales with clock frequency, down to a
from the device to detect when DOUT changes to
minimum clock frequency of f
CLK
= 100kHz. Table 8
logic 1, indicating that the data are valid.
summarizes the ratio of the clock input frequency
(f
CLK
) to data rate (f
DATA
), maximum data rate and
corresponding maximum clock input for the four
operating modes.
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