Datasheet

AINP
AINN
Z =14k
eff MO
W ´ (6.75MHz/f
D
)
ESDProtection
AVDDAGND
AVDD
AINP
9pF
AINN
AGND
S
1
S
1
S
2
ON
OFF
S
1
ON
OFF
S
2
t
SAMPLE MOD
=1/f
ESD
Protection
AVDDAVDD
VREFN
VREFP
AGND
AGND
VREFP VREFN
Z =
eff
´ (6.75MHz/f )
MOD
5.2kW
N
N=numberofactivechannels.
ADS1274
ADS1278
www.ti.com SBAS367F –JUNE 2007– REVISED FEBRUARY 2011
The ADS1274/78 uses switched-capacitor circuitry to
measure the input voltage. Internal capacitors are
charged by the inputs and then discharged. Figure 67
shows a conceptual diagram of these circuits. Switch
S
2
represents the net effect of the modulator circuitry
in discharging the sampling capacitor; the actual
implementation is different. The timing for switches S
1
and S
2
is shown in Figure 68. The sampling time
(t
SAMPLE
) is the inverse of modulator sampling
frequency (f
MOD
) and is a function of the mode, the
Figure 69. Effective Input Impedances
CLKDIV input, and CLK frequency, as shown in
Table 6.
VOLTAGE REFERENCE INPUTS
(VREFP, VREFN)
The voltage reference for the ADS1274/78 ADC is
the differential voltage between VREFP and VREFN:
V
REF
= (VREFP – VREFN). The voltage reference is
common to all channels. The reference inputs use a
structure similar to that of the analog inputs with the
equivalent circuitry on the reference inputs shown in
Figure 70. As with the analog inputs, the load
presented by the switched capacitor can be modeled
with an effective impedance, as shown in Figure 71.
However, the reference input impedance depends on
the number of active (enabled) channels in addition to
f
MOD
. As a result of the change of reference input
impedance caused by enabling and disabling
channels, the regulation and setting time of the
Figure 67. Equivalent Analog Input Circuitry
external reference should be noted, so as not to
affect the readings.
Figure 68. S
1
and S
2
Switch Timing for Figure 67
Table 6. Modulator Frequency (f
MOD
) Mode
Selection
MODE SELECTION CLKDIV f
MOD
High-Speed 1 f
CLK
/4
High-Resolution 1 f
CLK
/4
Figure 70. Equivalent Reference Input Circuitry
1 f
CLK
/8
Low-Power
0 f
CLK
/4
1 f
CLK
/40
Low-Speed
0 f
CLK
/8
The average load presented by the switched
capacitor input can be modeled with an effective
differential impedance, as shown in Figure 69. Note
that the effective impedance is a function of f
MOD
.
Figure 71. Effective Reference Impedance
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