Datasheet

) V
REF
2
23
* 1
* V
REF
2
23
* 1
v −V
REF
ǒ
2
23
2
23
* 1
Ǔ
100
0
Settling(%)
Conversions(1/f
DATA
)
0 2010 4030 6050 8070
FullySettledData
at76Conversions
(78Conversionsfor
High-Resolutionmode)
InitialValue
FinalValue
ADS1274
ADS1278
SBAS367F –JUNE 2007–REVISED FEBRUARY 2011 www.ti.com
Table 5. Ideal Output Code versus Input Signal
PHASE RESPONSE
INPUT SIGNAL V
IN
The ADS1274/78 incorporates a multiple stage, linear
(AINP – AINN) IDEAL OUTPUT CODE
(1)
phase digital filter. Linear phase filters exhibit
≥ +V
REF
7FFFFFh
constant delay time versus input frequency (constant
group delay). This characteristic means the time
000001h
delay from any instant of the input signal to the same
instant of the output data is constant and is
0 000000h
independent of input signal frequency. This behavior
results in essentially zero phase errors when
FFFFFFh
analyzing multi-tone signals.
800000h
SETTLING TIME
As with frequency and phase response, the digital
filter also determines settling time. Figure 66 shows
(1) Excludes effects of noise, INL, offset, and gain errors.
the output settling behavior after a step change on
the analog inputs normalized to conversion periods.
ANALOG INPUTS (AINP, AINN)
The X-axis is given in units of conversion. Note that
after the step change on the input occurs, the output
The ADS1274/78 measures each differential input
data change very little prior to 30 conversion periods.
signal V
IN
= (AINP – AINN) against the common
The output data are fully settled after 76 conversion
differential reference V
REF
= (VREFP – VREFN). The
periods for High-Speed and Low-Power modes, and
most positive measurable differential input is +V
REF
,
78 conversion periods for High-Resolution mode.
which produces the most positive digital output code
of 7FFFFFh. Likewise, the most negative measurable
differential input is –V
REF
, which produces the most
negative digital output code of 800000h.
For optimum performance, the inputs of the
ADS1274/78 are intended to be driven differentially.
For single-ended applications, one of the inputs
(AINP or AINN) can be driven while the other input is
fixed (typically to AGND or +2.5V). Fixing the input to
2.5V permits bipolar operation, thereby allowing full
use of the entire converter range.
While the ADS1274/78 measures the differential input
signal, the absolute input voltage is also important.
This value is the voltage on either input (AINP or
AINN) with respect to AGND. The range for this
voltage is:
Figure 66. Step Response
–0.1V < (AINN or AINP) < AVDD + 0.1V
If either input is taken below –0.4V or above
(AVDD + 0.4V), ESD protection diodes on the inputs
DATA FORMAT
may turn on. If these conditions are possible, external
The ADS1274/78 outputs 24 bits of data in twos
Schottky clamp diodes or series resistors may be
complement format.
required to limit the input current to safe values (see
the Absolute Maximum Ratings table).
A positive full-scale input produces an ideal output
code of 7FFFFFh, and the negative full-scale input
The ADS1274/78 is a very high-performance ADC.
produces an ideal output code of 800000h. The
For optimum performance, it is critical that the
output clips at these codes for signals exceeding
appropriate circuitry be used to drive the ADS1274/78
full-scale. Table 5 summarizes the ideal output codes
inputs. See the Application Information section for
for different input signals.
several recommended circuits.
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