Datasheet

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SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007
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7
TIMING CHARACTERISTICS: FRAME-SYNC FORMAT
SCLK
FSYNC
DOUT
DIN
t
DOHD
t
FPW
t
S
t
SF
t
SPW
t
SPW
t
FRAME
t
FPW
t
FS
t
DIHD
t
DDO
t
DIST
Bit 23 (MSB) Bit 22 Bit 21
t
DOPD
CLK
t
CPW
t
CPW
t
CF
t
CLK
TIMING REQUIREMENTS: FRAME-SYNC FORMAT
for T
A
= −40°C to +105°C and DVDD = 1.65V to 3.6V.
SYMBOL PARAMETER MIN TYP MAX UNIT
t
CLK
CLK period (1/f
CLK
) 37 10,000 ns
t
CPW
CLK positive or negative pulse width 15 ns
t
CF
Falling edge of CLK to falling edge of SCLK −0.35 t
CLK
0.35 t
CLK
ns
High-Speed mode 256 CLK periods
t
FRAME
Frame period (1/f
DATA
)
High-Resolution mode 256 or 512
(1)
CLK periods
t
FRAME
Frame period (1/f
DATA
)
Low-Power mode 256 or 512
(1)
CLK periods
t
FPW
FSYNC positive or negative pulse width 1 SCLK periods
t
FS
Rising edge of FSYNC to rising edge of SCLK 5 ns
t
SF
Rising edge of SCLK to rising edge of FSYNC 5 ns
SCLK period (SCLK must
High-Speed mode τ
FRAME
/64 τ
FRAME
periods
t
S
SCLK period (SCLK must
be continuously running)
High-Resolution mode τ
FRAME
/128 τ
FRAME
periods
t
S
be continuously running)
Low-Power mode τ
FRAME
/64 τ
FRAME
periods
t
SPW
SCLK positive or negative pulse width 0.4t
SCLK
0.6t
SCLK
ns
t
DOHD
(2)(3)
SCLK falling edge to old DOUT invalid (hold time) 5 ns
t
DOPD
(2)
SCLK falling edge to new DOUT valid (propagation delay) 12 ns
t
DDO
(2)
Valid DOUT to rising edge of FSYNC 0 ns
t
DIST
New DIN valid to falling edge of SCLK (setup time) 6 ns
t
DIHD
(3)
Old DIN valid to falling edge of SCLK (hold time) 6 ns
(1)
The ADS1271 automatically detects either frame period (only 256 or 512 allowed).
(2)
Load on DOUT = 20pF.
(3)
t
DOHD
(DOUT hold time) and t
DIHD
(DIN Hold time) are specified under opposite worst case conditions (digital supply voltage and ambient
temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is 4nS.