Datasheet

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SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007
www.ti.com
6
TIMING CHARACTERISTICS: SPI FORMAT
CLK
t
CPW
t
CLK
t
CPW
t
SD
t
S
t
DIST
t
DOHD
t
SPW
Bit 23 (MSB) Bit 22 Bit 21
t
SPW
t
DOPD
t
CD
t
DS
t
DDO
t
DIHD
•••
t
CONV
DRDY
SCLK
DOUT
DIN
TIMING REQUIREMENTS: SPI FORMAT
For T
A
= −40°C to +105°C and DVDD = 1.65V to 3.6V.
SYMBOL PARAMETER MIN TYP MAX UNIT
t
CLK
CLK period (1/f
CLK
) 37 10,000 ns
t
CPW
CLK positive or negative pulse width 15 ns
High-Speed mode 256 CLK periods
t
CONV
Conversion period (1/f
DATA
)
High-Resolution mode 512 CLK periods
t
CONV
Conversion period (1/f
DATA
)
Low-Power mode 512 CLK periods
t
CD
(1)
Falling edge of CLK to falling edge of DRDY 8 ns
t
DS
(1)
Falling edge of DRDY to rising edge of first SCLK to retrieve data 5 ns
t
DDO
(1)
Valid DOUT to falling edge of DRDY 0 ns
t
SD
(1)
Falling edge of SCLK to rising edge of DRDY 8 ns
t
S
(2)
SCLK period t
CLK
ns
t
SPW
SCLK positive or negative pulse width 12 ns
t
DOHD
(1)(3)
SCLK falling edge to old DOUT invalid (hold time) 5 ns
t
DOPD
(1)
SCLK falling edge to new DOUT valid (propagation delay) 12 ns
t
DIST
New DIN valid to falling edge of SCLK (setup time) 6 ns
t
DIHD
(3)
Old DIN valid to falling edge of SCLK (hold time) 6 ns
(1)
Load on DRDY and DOUT = 20pF.
(2)
For best performance, limit f
SCLK
/f
CLK
to ratios of 1, 1/2, 1/4, 1/8, etc.
(3)
t
DOHD
(DOUT hold time) and t
DIHD
(DIN Hold time) are specified under opposite worst case conditions (digital supply voltage and ambient
temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is 4nS.