Datasheet


SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007
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30
1.8V to 3.3V
(1)
Tie to
Either
DVDD
or GND
+5V
Differential
Inputs
50
Ω
50
Ω
50
Ω
50
Ω
50
Ω
100
Ω
+5V
+
+
50
Ω
10
µ
F
10
µ
F0.1
µ
F
0.47
µ
F
0.1
µ
F
+
0.1
µ
F
100pF
100pF
10
µ
F
+5V
1nF
100
µ
F
0.1
µ
F
0.1
µ
F
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VREFP
VREFN
DGND
DVDD
CLK
SCLK
DRDY/
FSYNC
DOUT
AINP
AINN
AGND
AVDD
MODE
FORMAT
SYNC/
PDWN
DIN
ADS1271
27MHz
Clock
Source
REF3125
100
Ω
1k
Ω
1k
Ω
10nF
OPA350
(2)
NOTE: (1) 1.8V recommended. (2) Recommended
circuit for reference noise filtering.
Figure 68. Basic Connection Drawing
+15V
(1)
NOTES:
(1) Bypass with 10
µ
Fand0.1
µ
F capacitors.
(2) 2.7nF for Low−Power mode.
−
15V
(1)
V
REF
V
IN
49.9
Ω
AINP
OPA1632
AINN
V
OCM
0.1
µ
F
1k
Ω
1k
Ω
1k
Ω
1k
Ω
49.9
Ω
1.5nF
(2)
1.5nF
(2)
Figure 69. Basic Differential Input Signal Interface
+15V
(1)
NOTES:
(1) Bypass with 10
µ
F and 0.1
µ
F capacitors.
(2) 10nF for Low−Power mode.
−
15V
(1)
V
REF
V
IN
OPA1632
49.9
Ω
AINP
AINN
V
ODIFF
=0.25
×
V
IN
V
OCOMM
=V
REF
V
OCM
0.1
µ
F
249
Ω
1k
Ω
249
Ω
1k
Ω
49.9
Ω
5.6nF
(2)
5.6nF
(2)
Figure 70. Basic Single-Ended Input Signal
Interface