Datasheet

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SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007
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MODULATOR OUTPUT
The ADS1271 incorporates a 6th-order, single-bit,
chopper-stabilized modulator followed by a multi-stage
digital filter, which yields the conversion results. The data
stream output of the modulator is available directly,
bypassing the internal digital filter. In this mode, an
external digital filter implemented in an ASIC, FPGA, or
similar device is required. To invoke the modulator output,
float the FORMAT pin and tie DIN to DVDD. DOUT then
becomes the modulator data stream output and SCLK
becomes the modulator clock output. The DRDY
/FSYNC
pin becomes an unused output and can be ignored. The
normal operation of the Frame-Sync and SPI interfaces is
disabled, and the functionality of SCLK changes from an
input to an output, as shown in Figure 66. Note that
modulator output mode is specified for the B grade device
only.
FORMAT
DIN
Modulator Data Output
Modulator Clock Output
(Float)
DOUT
DVDD
SCLK
Figure 66. Modulator Output (B-Grade Device)
In modulator output mode, the frequency of the SCLK
clock output depends on the mode selection of the
ADS1271. Table 12 lists the modulator clock output
frequency versus device mode.
Table 12. Modulator Output Clock Frequencies
MODE PIN
MODULATOR CLOCK OUTPUT
(SCLK)
0 f
CLK
/4
Float f
CLK
/4
1 f
CLK
/8
Figure 67 shows the timing relationship of the modulator
clock and data outputs.
SCLK
DOUT
Modulator
Clock Output
Modulator
Data Output
(10ns max)
Figure 67. Modulator Output Timing