Datasheet

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SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007
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27
DAISY-CHAINING
Multiple ADS1271s can be daisy-chained together to
simplify the serial interface connections. The DOUT of one
ADS1271 is connected to the DIN of the next ADS1271.
The first DOUT provides the output data and the last DIN
in the chain is connected to ground. A common SCLK is
used for all the devices in the daisy chain. Figure 64 shows
an example of a daisy chain with four ADS1271s.
Figure 65 shows the timing diagram when reading back in
the SPI format. It takes 96 SCLKs to shift out all the data.
In SPI format, it is recommended to tie all the
SYNC
/PDWN inputs together, which forces
synchronization of all the devices. It is only necessary to
monitor the DRDY output of one device when multiple
devices are configured this way.
In Frame-Sync format, all of the devices are driven to
synchronization by the FSYNC and SCLK inputs. However,
to ensure synchronization to the same f
CLK
cycle, it is
recommended to tie all SYNC
/PDWN inputs together.
The device clocks the SYNC
/PDWN pin on the falling edge
of f
CLK
. To ensure exact synchronization, the SYNC/PDWN
pin should transition on the rising edge of f
CLK
Since DOUT and DIN are both shifted on the falling edge
of SCLK, the propagation delay on DOUT creates the
setup time on DIN. Minimize the skew in SCLK to avoid
timing violations. See Mode Selection section for MODE
pin use when daisy-chaining.
The SPI format offers the most flexibility when
daisy-chaining because there is more freedom in setting
the SCLK frequency. The maximum number of ADS1271s
that can be daisy-chained is determined by dividing the
conversion time (1/f
DATA
) by the time needed to read back
all 24 bits (24 × 1/f
SCLK
).
Consider the case where:
f
CLK
= 27MHz
mode = High-Resolution (52,734SPS)
format = SPI
f
SCLK
= 27MHz
The maximum length of the daisy-chain is:
27MHz/(24 × 52,734SPS) = 21.3
Rounding down gives 21 as the maximum number of
ADS1271s that can be daisy-chained.
Daisy-chaining also works in Frame-Sync format, but the
maximum number of devices that can be daisy-chained is
less than when using the SPI format. The ratio between the
frame period and SCLK period is fixed, as shown in
Table 10. Using these values, the maximum number of
devices is two for High-Speed and Low-Power modes, and
five for High-Resolution mode.
ADS1271
4
DIN
SCLK
SCLK
SYNC
DOUT
ADS1271
3
DOUT
ADS1271
2
DOUT
ADS1271
1
DOUT
SYNC
DIN
SCLK
SYNC
DIN
SCLK
SYNC
DIN
SCLK
SYNC
DRDY
Figure 64. Example of SPI-Format, Daisy-Chain Connection for Multiple ADS1271s
DRDY
SCLK 1
ADS1271
1
Bit 23 (MSB)
ADS1271
1
Bit 0 (LSB)
ADS1271
4
Bit 0 (LSB)
ADS1271
2
Bit 23 (MSB)
ADS1271
4
Bit 23 (MSB)
24 25 73 96
DOUT
Figure 65. Timing Diagram for Example in Figure 64 (SPI Format)