Datasheet

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SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007
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26
FRAME-SYNC SERIAL INTERFACE
Frame-Sync format is similar to the interface often used on
audio ADCs. It operates in slave fashion—the user must
supply framing signal FSYNC (similar to the left/right clock
on stereo audio ADCs) and the serial clock SCLK (similar
to the bit clock on audio ADCs). The data is output MSB
first or left-justified. When using Frame-Sync format, the
CLK, FSYNC and SCLK inputs must be synchronized
together, as described in the following sub-sections.
SCLK (Frame-Sync Format)
The serial clock (SCLK) features a Schmitt-triggered input
and shifts out data on DOUT on the falling edge. It also
shifts in data on the falling edge on DIN when this pin is
being used for daisy-chaining. Even though SCLK has
hysteresis, it is recommended to keep SCLK as clean as
possible to prevent glitches from accidentally shifting the
data. When using Frame-Sync format, SCLK must run
continuously. If it is shut down, the data readback will be
corrupted. Frame-Sync format requires a specific
relationship between SCLK and FSYNC, determined by
the mode shown in Table 10. When the device is
configured for modulator output, SCLK becomes the
modulator clock output (see the Modulator Output
section).
Table 10. SCLK Period When Using Frame-Sync
Format
MODE REQUIRED SCLK PERIOD
High-Speed τ
FRAME
/64
High-Resolution τ
FRAME
/128
Low-Power τ
FRAME
/64
DRDY/FSYNC
In Frame-Sync format, this pin is used as the FSYNC input.
The frame-sync input (FSYNC) sets the frame period. The
required FSYNC periods are shown in Table 11. For
High-Speed mode, the FSYNC period must be 256 CLK
periods. For both High-Resolution and Low-Power modes,
the FSYNC period can be either 512 or 256 CLK periods;
the ADS1271 will automatically detect which is being
used. If the FSYNC period is not the proper value, data
readback will be corrupted. It is recommended that
FSYNC be aligned with the falling edge of SCLK.
Table 11. FSYNC Period
MODE REQUIRED FSYNC PERIOD
High-Speed 256 CLK Periods
High-Resolution 256 or 512 CLK periods
Low-Power 256 or 512 CLK periods
DOUT
The conversion data is shifted out on DOUT. The MSB
data becomes valid on DOUT on the CLK rising edge prior
to FSYNC going high. The subsequent bits are shifted out
with each falling edge of SCLK. If daisy-chaining, the data
shifted in using DIN will appear on DOUT after all 24 bits
have been shifted out. When the device is configured for
modulator output, DOUT becomes the modulator data
output (see the Modulator Output section).
DIN
This input is used when multiple ADS1271s are to be
daisy-chained together. It can be used with either SPI or
Frame-Sync formats. Data is shifted in on the falling edge
of SCLK. When using only one ADS1271, tie DIN low.See
the Daisy-Chaining section for more information.