Datasheet

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SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007
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21
POWER-DOWN AND OFFSET CALIBRATION
In addition to controlling synchronization, the
SYNC
/PDWN pin also serves as the control for
Power-Down mode and offset calibration. To enter this
mode, hold the SYNC/PDWN pin low for at least 2
19
CLK
periods. While in Power-Down mode, both the analog and
digital circuitry are completely deactivated. The digital
inputs are internally disabled so that is not necessary to
shut down CLK and SCLK. To exit Power-Down mode,
return SYNC
/PDWN high on the rising edge of CLK.
The ADS1271 uses a chopper-stabilized modulator to
provide inherently very low offset drift. To further minimize
offset, the ADS1271 automatically performs an offset
self-calibration when exiting Power-Down mode. When
power down completes, the offset self-calibration begins
with the inputs AINP and AINN automatically
disconnected from the signal source and internally shorted
together. There is no need to modify the signal source
applied to the analog inputs during this calibration.
It is critical for the reference voltage to be stable when
exiting Power-Down mode; otherwise, the calibration will
be corrupted.
The offset self-calibration only removes offset errors internal
to the device, not offset errors due to external sources.
NOTE: When an offset self-calibration is performed, the
resulting offset value will vary each time within the
peak-to-peak noise range of the converter. In High-Speed
mode, this is typically 178 LSBs.
The offset calibration value is cleared whenever the device
mode is changed (for example, from High-Speed mode to
High-Resolution mode).
When using the SPI format, DRDY
will stay high after
exiting Power-Down mode while the digital filter settles, as
shown in Figure 52.
When using the Frame-Sync format, DOUT will stay low
after exiting Power-Down mode while the digital filter
settles, as shown in Figure 53.
NOTE: In Power-Down mode, the inputs of the ADS1271
must be driven (do not float) and the device drives the
outputs driven to a DC level.
Status
CLK
Converting Sync Power Down Converting
Post−Calibration
Data Ready
Offset Cal and Filter Settling
DRDY
••••••
SYNC/PDWN
t
PDWN
t
OFS
SYMBOL
t
PDWN pulse width to enter Power−Down mode
2
19
CLK periods
t
OFS
Time for offset calibration and filter settling
256
Conversions
(1/f
DATA
)
MIN TYP MAX UNITSDESCRIPTION
SYNC/PDWN
Figure 52. Power-Down Timing for SPI format
SYMBOL
t
PDWN
pulse width to enter Power−Down mode
2
19
CLK periods
t
OFS
Time for offset calibration and filter settling
257256
Conversions
(1/f
DATA
)
MIN TYP MAX UNITSDESCRIPTION
Status
CLK
FSYNC
DOUT
••••••
SYNC/PDWN
t
OFS
t
PDWN
Converting Sync Power Down Converting
Post−Calibration Data
Offset Cal and Filter Settling
SYNC/PDWN
Figure 53. Power-Down Timing for Frame-Sync Format