Datasheet

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SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007
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20
SYNCHRONIZATION
The SYNC/PDWN pin has two functions. When pulsed, it
synchronizes the start of conversions and, if held low for
more than 2
19
CLK cycles (t
SYN
), places the ADS1271 in
Power-Down mode. The SYNC
/PDWN pin can be left high
for continuous data acquisition. See the Power-Down and
Offset Calibration section for more details.
The ADS1271 can be synchronized by pulsing the
SYNC
/PDWN pin low and then returning the pin high.
When the pin goes low, the conversion process is stopped,
and the internal counters used by the digital filter are reset.
When the SYNC
/PDWN pin is returned high, the
conversion process is restarted. Synchronization allows
the conversion to be aligned with an external event; for
example, the changing of an external multiplexer on the
analog inputs, or by a reference timing pulse.
The SYNC
/PDWN pin is capable of synchronizing multiple
ADS1271s to within the same CLK cycle. Figure 50 shows
the timing requirement of SYNC/PDWN and CLK in SPI
format.
Figure 51 shows the timing requirement for Frame-Sync
format.
After synchronization, indication of valid data depends on
the whether SPI or Frame-Sync format was used.
In the SPI format, DRDY
goes high as soon as
SYNC
/PDWN is taken low, as shown in Figure 50. After
SYNC
/PDWN is returned high, DRDY stays high while the
digital filter is settling. Once valid data is ready for retrieval,
DRDY goes low.
In the Frame-Sync format, DOUT goes low as soon as
SYNC
/PDWN is taken low, as shown in Figure 51. After
SYNC
/PDWN is returned high, DOUT stays low while the
digital filter is settling. Once valid data is ready for retrieval,
DOUT begins to output valid data. For proper
synchronization, FSYNC, SCLK, and CLK must be
established before taking SYNC
/PDWN high, and must
then remain running.
CLK
DRDY
SYNC/PDWN
t
NDR
t
SYN
t
CSHD
t
SCSU
SYMBOL
t
SCSU
Synchronize pulse width
2
18
5
10
1
CLK periods
t
CSHD
Time for new data to be ready 128
Conversions (1/f
DATA
)
MIN TYP MAX UNITSDESCRIPTION
t
SYN
SYNC/PWDN to CLK setup time
ns
t
NDR
CLK to SYNC/PWDN hold time
ns
Figure 50. Synchronization Timing for SPI format
FSYNC
Valid Data
DOUT
t
NDR
SYMBOL
t
SYN
Synchronize pulse width
2
18
1
5
10
CLK periods
t
NDR
Time for new data to be ready
128 129
Conversions (1/f
DATA
)
MIN TYP MAX UNITSDESCRIPTION
t
SCSU
SYNC/PWDN to CLK setup time ns
t
CSHD CLK to SYNC/PWDN hold time
ns
CLK
SYNC/PDWN
t
SYN
t
CSHD
t
SCSU
Figure 51. Synchronization Timing for Frame-Sync Format