Datasheet

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SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007
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18
CLOCK INPUT (CLK)
The ADS1271 requires an external clock signal to be
applied to the CLK input pin. As with any high-speed data
converter, a high-quality, low-jitter clock is essential for
optimum performance. Crystal clock oscillators are the
recommended clock source. Make sure to avoid excess
ringing on the clock input; keeping the clock trace as short
as possible using a 50Ω series resistor will help.
The ratio between the clock frequency and output data rate
is a function of the mode and format. Table 3 shows the
ratios when the SPI format is selected. Also included in this
table is the typical CLK frequency and the corresponding
data rate. When High-Speed mode is used, each
conversion takes 256 CLK periods. When
High-Resolution or Low-Power modes are selected, the
conversions take 512 CLK periods.
Table 4 shows the ratios when the Frame-Sync format is
selected. When using the Frame-Sync format in either
High-Resolution or Low-Power mode, the f
CLK
/f
DATA
ratio
can be 256 or 512. The ADS1271 automatically detects
which ratio is being used. Using a ratio of 256 allows the
CLK frequency to be reduced by a factor of two while
maintaining the same data rate. The output data rate
scales with the clock frequency. See the Serial Interface
section for more details on the Frame-Sync operation.
Table 3. Clock Ratios for SPI Format
MODE SELECTION f
CLK
/f
DATA
TYPICAL f
CLK
(MHz) " CORRESPONDING DATA RATE (SPS)
High-Speed 256 27 " 105,469
High-Resolution 512 27 " 52,734
Low-Power 512 27 " 52,734
Table 4. Clock Ratios for Frame-Sync Format
MODE SELECTION f
CLK
/f
FRAME
TYPICAL f
CLK
(MHz) " CORRESPONDING DATA RATE (SPS)
High-Speed 256 27 " 105,469
High-Resolution
256 13.5 " 52,734
High-Resolution
512 27 " 52,734
Low-Power
256 13.5 " 52,734
Low-Power
512 27 " 52,734