Datasheet

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SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007
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16
ANALOG INPUTS (AINP, AINN)
The ADS1271 measures the differential input signal
V
IN
= (AINP – AINN) against the differential reference
V
REF
= (VREFP – VREFN). The most positive measurable
differential input is +V
REF
, which produces the most
positive digital output code of 7FFFFFh. Likewise, the
most negative measurable differential input is −V
REF
,
which produces the most negative digital output code of
800000h.
While the ADS1271 measures the differential input signal,
the absolute input voltage is also important. This is the
voltage on either input (AINP or AINN) with respect to
AGND. The range for this voltage is:
−0.1V < (AINN or AINP) < AVDD +0.1V
If either input is taken below –0.4V or above (AVDD + 0.4),
ESD protection diodes on the inputs may turn on.
If these conditions are possible, external Schottky clamp
diodes or series resistors may be required to limit the input
current to safe values (see Absolute Maximum Ratings).
The ADS1271 uses switched-capacitor circuitry to
measure the input voltage. Internal capacitors are charged
by the inputs and then discharged. Figure 44 shows a
conceptual diagram of these circuits. Switch S2
represents the net effect of the modulator circuitry in
discharging the sampling capacitor; the actual
implementation is different. The timing for switches S1 and
S2 is shown in Figure 45. The sampling time (t
SAMPLE
) is
the inverse of modulator sampling frequency (f
MOD
) and is
a function of the mode, format, and frequency of CLK, as
shown in Table 2. When using the Frame-Sync format with
High-Resolution or Low-Power modes, the ratio between
f
MOD
and f
CLK
depends on the frame period that is set by the
FSYNC input.
ESD Protection
AVDDAGND
AVDD
AINP
9pF
AINN
AGND
S
1
S
1
S
2
Figure 44. Equivalent Analog Input Circuitry
ON
OFF
S1
ON
OFF
S2
t
SAMPLE
=1/f
MOD
Figure 45. S1 and S2 Switch Timing for Figure 44
Table 2. Modulator Frequency for the Different
Mode and Format Settings
MODE
INTERFACE
FORMAT
f
MOD
High-Speed SPI or Frame-Sync f
CLK
/4
High-Resolution
SPI f
CLK
/4
High-Resolution
Frame-Sync f
CLK
/4 or f
CLK
/2
Low-Power
SPI f
CLK
/8
Low-Power
Frame-Sync f
CLK
/8 or f
CLK
/4
The average load presented by the switched capacitor
input can be modeled with an effective differential
impedance, as shown in Figure 46. Note that the effective
impedance is a function of f
MOD
.
AINP
AINN
Zeff = 16.4k
Ω×
(6.75MHz/f
MOD
)
Figure 46. Effective Input Impedances
The ADS1271 is a very high-performance ADC. For
optimum performance, it is critical that the appropriate
circuitry be used to drive the ADS1271 inputs. See the
Application Information section for the recommended
circuits.