Datasheet

SCLK
CS
DIN
DOUT
t
SCLK
t
CSSC
t
DIHD
t
CSH
t
CSDOD
t
DIST
t
SPWH
t
SPWL
t
CSDOZ
t
DOHD
t
DOPD
B7 B6 B5 B4 B3 B2 B1 B0
B7
B6 B5
B4
B3
B2 B1
B0
ADS1259
SBAS424D –JUNE 2009– REVISED AUGUST 2011 www.ti.com
SPI TIMING CHARACTERISTICS
Figure 1. Serial Interface Timing
TIMING REQUIREMENTS: SERIAL INTERFACE TIMING
At T
A
= –40°C to +105°C and DVDD = 2.7V to 5.25V, unless otherwise noted.
SYMBOL DESCRIPTION MIN MAX UNIT
t
CSSC
CS low to first SCLK: setup time
(1)
50 ns
t
SCLK
SCLK period 1.8 t
CLK
(2)
t
SPWH
SCLK pulse width: high 90 ns
90 ns
t
SPWL
SCLK pulse width: low
(3)
2
16
t
CLK
t
DIST
Valid DIN to SCLK falling edge: setup time 35 ns
t
DIHD
Valid DIN to SCLK falling edge: hold time 20 ns
t
DOPD
SCLK rising edge to valid new DOUT: propagation delay
(4)
60 ns
t
DOHD
SCLK rising edge to DOUT invalid: hold time 0 ns
t
CSDOD
CS low to DOUT driven: propagation delay
(4)
0 40 ns
t
CSDOZ
CS high to DOUT Hi-Z: propagation delay 20 ns
t
CSH
CS high pulse 20 t
CLK
(1) CS can be tied low.
(2) t
CLK
= 1/f
CLK
.
(3) Holding SCLK low longer than 2
16
× t
CLK
cycles resets the SPI interface (enabled by SPI register bit).
(4) DOUT load = 20pF || 100kΩ to DGND.
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