Datasheet

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AINP
AINN
RESETPWDN/
START
SYNCOUT
CS
SCLK
DIN
DOUT
DRDY
AVDD
AVSS
VREFN
VREFP
REFOUT
DVDD
DGND
BYPASS
XTAL2
XTAL1/CLKIN
ADS1259
ADS1259
www.ti.com SBAS424D –JUNE 2009– REVISED AUGUST 2011
PIN CONFIGURATION
PW PACKAGE
TSSOP-20
(TOP VIEW)
ADS1259 Terminal Functions
PIN NAME PIN # FUNCTION DESCRIPTION
AINP 1 Analog input Positive analog input
AINN 2 Analog input Negative analog input
RESET/PWDN 3 Digital input Reset/Power-Down; reset is active low; hold low for power-down
START 4 Digital input Start conversions, active high
SYNCOUT 5 Digital output Sync clock output (f
CLK
/8)
CS 6 Digital input SPI chip-select, active low
SCLK 7 Digital input SPI clock input
DIN 8 Digital input SPI data input
DOUT 9 Digital output SPI data output
DRDY 10 Digital output Data ready output, active low
Internal oscillator: DGND
XTAL1/CLKIN 11 Digital input External clock: clock input
Crystal oscillator: external crystal1
XTAL2 12 Digital External crystal2, otherwise no connection
BYPASS 13 Analog Core voltage bypass
DGND 14 Digital Digital ground
DVDD 15 Digital Digital power supply
REFOUT 16 Analog output Positive reference output
VREFP 17 Analog input Positive reference input
VREFN 18 Analog input Negative reference input
AVSS 19 Analog Negative analog power supply and negative reference output
AVDD 20 Analog Positive analog power supply
Copyright © 2009–2011, Texas Instruments Incorporated 5