Datasheet

ADS1259

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SBAS424D –JUNE 2009– REVISED AUGUST 2011

The operation of the ADS1259 is controlled through a set of registers. Collectively, the registers contain all the

information needed to configure the part, such as data rate, calibration, etc. Table 20 shows the register map.

Table 20. Register Map

RESET

ADDRESS REGISTER VALUE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

0h CONFIG0 10XX0101b 1 0 ID1 ID0 0 RBIAS 0 SPI

1h CONFIG1 00001000b FLAG CHKSUM 0 SINC2 EXTREF DELAY2 DELAY1 DELAY0

2h CONFIG2 XX000000b DRDY EXTCLK SYNCOUT PULSE 0 DR2 DR1 DR0

3h OFC0 00000000b OFC07 OFC06 OFC05 OFC04 OFC03 OFC02 OFC01 OFC00

4h OFC1 00000000b OFC15 OFC14 OFC13 OFC12 OFC11 OFC10 OFC09 OFC08

5h OFC2 00000000b OFC23 OFC22 OFC21 OFC20 OFC19 OFC18 OFC17 OFC16

6h FSC0 00000000b FSC07 FSC06 FSC05 FSC04 FSC03 FSC02 FSC01 FSC00

7h FSC1 00000000b FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC09 FSC08

8h FSC2 01000000b FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16

CONFIG0: CONFIGURATION REGISTER 0 (Address = 0h)

7 6 5 4 3 2 1 0

1 0 ID1 ID0 0 RBIAS 0 SPI

Reset value = 10XX0101b.

Bit 7 Reserved (read-only)

Always returns '1'.

Bit 6 Reserved (read-only)

Always returns '0'.

Bits 5-4 ID[1:0]: Factory-programmed identification bits (read-only)

(Note that these bits may change without notification.)

Bit 3 Reserved

Always write '0'.

Bit 2 RBIAS: Internal reference bias

0 = Internal reference bias disabled

1 = Internal reference bias enabled (default)

Bit 1 Reserved

Always write '0'.

Bit 0 SPI: SCLK timeout of SPI interface

0 = SPI timeout disabled

1 = SPI timeout enabled (default), when SCLK is held low for 2

clock cycles