Datasheet

FinalOutputData=(Input OFC[2:0])- ´
FSC[2:0]
400000h
Modulator
AINP
AINN
Digital
Filter
S
OFC
Register
FinalOutput
OutputData
Clippedto24Bits
´
+
-
FSCRegister
400000h
ADS1259
SBAS424D –JUNE 2009– REVISED AUGUST 2011 www.ti.com
Table 11. Offset Calibration Values
OFFSET AND FULL-SCALE CALIBRATION
REGISTERS
OFC REGISTER FINAL OUTPUT CODE
(1)
7FFFFFh 800001h
The conversion data are scaled by offset and gain
registers before yielding the final output code. As
000001h FFFFFFh
shown in Figure 55, the output of the digital filter is
000000h 000000h
first subtracted by the offset register (OFC) and then
FFFFFFh 000001h
multiplied by the full-scale register (FSC). Equation 8
800001h 7FFFFFh
shows the scaling:
(1) Ideal output code excluding noise and inherent offset error.
FSC[2:0] Registers
(8)
The full-scale calibration is a 24-bit word, composed
The values of the offset and full-scale registers are
of three 8-bit registers, as shown in Table 14. The
set by writing to them directly, or they are set by
full-scale calibration value is 24-bit, straight binary,
calibration commands.
normalized to 1.0 at code 400000h. Table 12
summarizes the scaling of the full-scale register. A
OFC[2:0] Registers
register value of 400000h (default value) has no gain
The offset calibration is a 24-bit word, composed of
correction (gain = 1). Note that while the gain
three 8-bit registers, as shown in Table 13. The offset
calibration register value corrects gain errors above 1
is in twos complement format with a maximum
(gain correction < 1), the full-scale range of the
positive value of 7FFFFFh and a maximum negative
analog inputs cannot exceed 105% full-scale to avoid
value of 800000h. This value is subtracted from the
input overload.
conversion data. A register value of 00000h has no
offset correction (default value). Note that while the
Table 12. Full-Scale Calibration Register Values
offset calibration register value can correct offsets
FSC REGISTER GAIN FACTOR
ranging from –FS to +FS (as Table 11 shows), to
800000h 2.0
avoid input overload, the analog inputs cannot
exceed 105% full-scale.
400000h 1.0
200000h 0.5
000000h 0
Figure 55. Calibration Block Diagram
Table 13. Offset Calibration Word
REGISTER BYTE BIT ORDER
OFC0 LSB B7 B6 B5 B4 B3 B2 B1 B0 (LSB)
OFC1 MID B15 B14 B13 B12 B11 B10 B9 B8
OFC2 MSB B23 (MSB) B22 B21 B20 B19 B18 B17 B16
Table 14. Full-Scale Calibration Word
REGISTER BYTE BIT ORDER
FSC0 LSB B7 B6 B5 B4 B3 B2 B1 B0 (LSB)
FSC1 MID B15 B14 B13 B12 B11 B10 B9 B8
FSC2 MSB B23 (MSB) B22 B21 B20 B19 B18 B17 B16
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