Datasheet

STARTPin
DRDY
Halted
Single
Conversion
Halted
Single
Conversion
OROR
STARTSTART
DRDY
DOUT
Settled
Data
START
Pin
START
Command
or
t
SET
(1)
7thFallingSCLKEdgeofOpcode
V =AINP AINN-
IN
SettledV
IN
ADS1259
SBAS424D –JUNE 2009– REVISED AUGUST 2011 www.ti.com
Pulse Control Mode (PULSE Bit = 1) Settling Time Using START
In the Pulse Control mode, the ADS1259 performs a When START goes high (via pin or command) a
single conversion when either the START pin is taken delay may be programmed before the conversion
high or when the START command is sent. As seen filter cycle begins. The programmable delay may be
in Figure 52, DRDY goes high when the conversion is useful to provide time for external circuits (such as
started. When the conversion is complete, DRDY after an external signal mux change), before the
goes low and further conversions are halted. To start reading is started. Register bits DELAY[2:0] set the
a new conversion, transition the START pin back to initial delay time as shown in Table 8.
high, or transmit the START opcode again.
Table 8. Initial START Delay
DELAY[2:0] t
DELAY
(t
CLK
) t
DELAY
(µs)
(1)
000 0 0
001 64 8.68
010 128 17.4
011 256 34.7
100 512 69.4
101 1024 139
110 2048 278
111 4096 556
(1) START opcode command takes effect on the seventh SCLK
falling edge.
(1) f
CLK
= 7.3728MHz.
Figure 52. Pulse Control Mode
After the programmable delay, the digital filter is reset
and a new conversion is started. DRDY goes low
when data are ready. There is no need to ignore or
CONVERSION SETTLING TIME
discard data; the data are completely settled. The
total time to perform the first conversion is the sum of
The ADS1259 features a digital filter architecture in
the programmable delay time and the settling of the
which settling time can be traded for wide filter
digital filter. That is, the value of Table 8 and Table 9
notches, resulting in improved line-cycle rejection.
combined. Figure 53 shows the timing and Table 9
This trade-off is determined by the selection of the
shows the settling time with programmable delay
sinc
1
or sinc
2
filter. The sinc
1
filter settles in a single
equal to '0'.
cycle while the sinc
2
filter provides wide-width filter
notches. The settling time of the ADS1259 is different
Table 9. Settling Time Using START
if START is used to begin conversions or if the
ADS1259 is free-running the conversions. These
SETTLING TIME (t
SET
) (ms)
(1)
DATA RATE
modes are explained in the Settling Time Using
(SPS) sinc
1
sinc
2
START and Settling Time While Continuously
10 100 200
Converting sections.
16.6 60.3 120
50 20.3 40.4
60 17.0 33.7
400 2.85 5.42
1200 1.18 2.10
3600 0.632 0.980
14,400 0.424 0.563
(1) f
CLK
= 7.3728MHz, DELAY[2:0] = 000.
(1) t
SET
= initial start delay plus the new conversion cycle time.
Figure 53. Data Retrieval Time After START
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