Datasheet

SCLK
RESETPWDN/
t
LOW
t
RHSC
CLK
DVDD
InternalReset
1Vnom
AVDD AVSS-
3.5Vnom
2
16
t´
CLK
ADS1259Operational
ADS1259
SBAS424D –JUNE 2009– REVISED AUGUST 2011 www.ti.com
RESET/PWDN RESET
The RESET/PWDN pin has two functions: device There are three methods to reset the ADS1259: cycle
power-down and device reset. Momentarily holding the power supplies, take RESET/PWDN low, or send
the pin low resets the device and holding the pin low the RESET opcode command.
for 2
16
f
CLK
cycles activates the Power-Down mode.
When using the RESET/PWDN pin, take it low to
force a reset. Make sure to follow the minimum pulse
POWER-DOWN MODE
width timing specifications before taking the RESET
pin back high.
In power-down mode, internal circuit blocks are
disabled (including the oscillator, reference, and SPI)
The RESET command takes effect on the eighth
and the device enters a micro-power state. To
falling SCLK edge of the opcode command. On reset,
engage power-down mode, hold the RESET/PWDN
the configuration registers are initialized to the default
pin low for 2
16
f
CLK
cycles. Note that the register
states and the conversion cycle restarts. After reset,
contents are not saved because they are reset when
allow eight f
CLK
cycles before communicating to the
RESET/PWDN goes high.
ADS1259. Note that when using the reset command,
the SPI interface itself may require reset before
Keep the digital inputs at defined V
IH
or V
INL
logic
accepting the command. See the SPI Timing
levels (do not 3-state). To minimize power-supply
Characteristics section for details.
leakage current, disable the external clock. Note that
the ADS1259 digital outputs remain active in
power-down. The analog signal inputs may float. POWER-ON SEQUENCE
To exit power-down, take RESET/PWDN high. Wait The ADS1259 has three power supplies: AVDD,
2
16
f
CLK
cycles before communicating to the AVSS, and DVDD. The supplies can be sequenced in
ADS1259, as shown in Figure 48. any order but be sure that at any time the analog
inputs do not exceed AVDD or AVSS and the digital
inputs do not exceed DVDD. After the last power
supply has crossed the respective power-on
threshold, 2
16
f
CLK
cycles are counted before
releasing the internal reset. After the internal reset is
released, the ADS1259 is ready for operation.
Figure 49 shows the power-on sequence of the
ADS1259.
Figure 48. RESET/PWDN Timing
Table 6. Timing Characteristics for Figure 48
SYMBOL DESCRIPTION MIN UNIT
t
LOW
Pulse width low for reset 4 t
CLK
t
LOW
Pulse width low for power-down 2
16
t
CLK
t
RHSC
Reset high to SPI communication start 8 t
CLK
t
RHSC
Exit power-down to SPI communication start 2
16
t
CLK
Figure 49. Power-On Sequence
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