Datasheet

XTAL1/CLKIN
XTAL2
External
Clock
50W
C
1
Crystal
(7.3728MHz)
XTAL1/CLKIN
XTAL2
C
1 2
,C :5pFto20pF
C
2
ADS1259
www.ti.com SBAS424D –JUNE 2009– REVISED AUGUST 2011
External Clock
SYNCOUT
Figure 46 shows the external clock connection. The
SYNCOUT is a digital output pin intended to
clock is applied to XTAL1/CLKIN and XTAL2 floats.
synchronize the chopping frequency of the PGA280
Make sure a clean clock input is applied to the
to the sampling frequency of the ADS1259.
ADS1259, free of overshoot and glitches. A series
Synchronizing the PGA280 to the ADS1259 places
resistor often helps to reduce overshoot and should
the PGA280 chopped 1/f noise at an exact null in the
be placed close to the driving end of the clock
ADS1259 frequency response, where the PGA280 1/f
source.
noise is rejected.
SYNCOUT frequency is equal to the ADS1259 clock
rate divided by 8 (f
SYNCOUT
= f
CLK
/8). The output clock
is enabled by the register bit SYNCOUT. Disabling
the output stops the clock but the output remains
actively driven low. In power-down mode, the
SYNCOUT output becomes an input. As with all
digital inputs, the pin must not be allowed to float. An
Figure 46. External Clock Connection
external 1MΩ pull-down resistor is recommended to
ground the input in power-down mode.
Crystal Oscillator
The SYNCOUT clock is reset when START is
received and whenever registers CONFIG[2:0] are
Figure 47 shows the crystal oscillator connection. The
changed. Connect SYNCOUT to the PGA280
crystal connects to XTAL1/CLKIN and XTAL2 and the
SYNCIN pin through a 4.7kΩ series resistor. Place
capacitors connect to ground. The crystal and
the resistor as close as possible to the ADS1259
capacitors should be placed close to the device pins
SYNCOUT pin.
with short, direct traces. Neither the XTAL1/CLKIN
nor the XTAL2 pins can be used to drive any other
logic. Table 5 lists the recommended crystal for the
SLEEP MODE
ADS1259. If using other crystals, verify the oscillator
SLEEP mode is started by sending the SLEEP
start-up behavior.
command. In SLEEP mode, the device enters a
reduced power state and only a minimum of circuitry
is kept active. The WAKEUP command exits the
SLEEP mode and after which 512 f
CLK
cycles are
counted before the ADS1259 is ready for
communication. The register settings are unaffected
in SLEEP.
SLEEP does not change the RBIAS register bit. For
quick conversions after WAKEUP, keep the internal
Figure 47. Crystal Connection
reference bias on before entering SLEEP. Otherwise,
after exiting SLEEP mode, allow time for the
reference to settle. Alternatively, to minimize power
Table 5. Recommended Crystal
consumption during SLEEP, set the internal reference
MANUFACTURER FREQUENCY PART NUMBER
bias off prior to engaging SLEEP. Note that in SLEEP
ECS 7.3728MHz ECS-73-18-10
mode the SPI timeout function is disabled.
BYPASS
The digital core of the ADS1259 is powered by an
internal low dropout regulator (LDO). The DVDD
supply is the LDO input and the BYPASS pin is the
LDO output. A 1μF capacitor must be connected from
the LDO output to DGND. No other load current
should be drawn from the BYPASS pin.
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