Datasheet

½H = H (f) H (f) =
(f)
sinc sinc
½ ½ ½ ´ ½ ½
5
N
5
sin
512 f´p
f
CLK
64 sin´
8 fp ´
f
CLK
´
sin
512 R f´p ´
f
CLK
R sin´
512 fp ´
f
CLK
N
Analog
Modulator
sinc
5
Filter
(decimateby64)
sinc Filter
1
f /512
CLK
ModulatorRate=f /8
CLK
sinc Filter
2
DR[2:0]RegisterBits
(ProgramDecimation)
Output
DataRate=f /(R )
CLK
512´
SINC2RegisterBit
(0=sinc )
1
ADS1259
SBAS424D –JUNE 2009– REVISED AUGUST 2011 www.ti.com
DIGITAL FILTER The SINC2 register bit selects either the sinc
1
or sinc
2
filter. The sinc
1
filter settles in one conversion cycle
The programmable low-pass digital filter receives the
while the sinc
2
filter settles in two conversion cycles.
modulator output and produces a high-resolution
However, the sinc
2
filter has the benefit of wider
digital output. By adjusting the amount of filtering,
frequency notches which improve line cycle rejection.
tradeoffs can be made between resolution and data
rate: filter more for higher resolution, filter less for
FREQUENCY RESPONSE
higher data rate.
The low-pass digital filter sets the overall frequency
The filter consists of two sections: a fixed decimation
response of the ADS1259. The filter response is the
sinc
5
filter followed by a variable decimation filter,
product of the fixed and programmable filter sections,
configurable as sinc
1
or sinc
2
, as illustrated in
and is given by Equation 5:
Figure 39. The sinc
5
filter has fixed decimation of 64
and reduces the data rate of the modulator from
f
CLK
/8 to f
CLK
/512. The second filter stage receives the
data from the sinc
5
filter. The second filter stage has
programmable averaging (or decimation) and can be
configured in either sinc
1
or sinc
2
mode. The
decimation ratio of this stage sets the final output
data rate. As detailed in Table 3, the DR[2:0] register
bits program the decimation ratio and the final output
data rate. The output data rates are identical for both
where:
sinc
1
and sinc
2
filters.
N = 1 (sinc
1
)
Table 3. Decimation Ratio of Final Filter Stage
N = 2 (sinc
2
)
R = Decimation ratio (refer to Table 3) (5)
DR[2:0] REGISTER DECIMATION
BITS RATIO (R) DATA RATE (SPS)
The digital filter attenuates noise on the modulator
111 1 14400
output, including noise from within the ADS1259 and
110 4 3600
external noise present within the ADS1259 input
101 12 1200
signal. Adjusting the filtering by changing the
decimation ratio used in the programmable filter
100 36 400
changes the filter bandwidth. With a higher number of
011 240 60
decimation, the bandwidth is reduced and more noise
010 288 50
is attenuated.
001 864 16.6
000 1440 10
Figure 39. Block Diagram of Digital Filter
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