Datasheet

Programmable
DigitalFilter
2.5V
Reference
DS
Modulator
VREFP VREFN
AVSS
DGND
AINP
AINN
XTAL2
XTAL1/CLKIN
Control
and
Serial
Interface
Clock
Generator
Out-of-Range
Detection
RESETPWDN/
DRDY
SCLK
DIN
START
CS
DOUT
Calibration
Engine
f /8
CLK
SYNCOUTDVDD
LDO
BYPASS
+1.8V
(DigitalCore)
FLAG
AVDD
REFOUT
ADS1259
ADS1259
SBAS424D –JUNE 2009– REVISED AUGUST 2011 www.ti.com
OVERVIEW
The ADS1259 is a high-linearity, low drift The digital filter receives the modulator signal and
analog-to-digital converter (ADC) designed for the provides the digital output. The filter consists of a
needs of industrial process control, precision fifth-order sinc filter followed by a programmable
instrumentation, and similar applications. The averager, selectable as either a sinc
1
or sinc
2
. In
converter provides high-resolution, 24-bit output data sinc
1
mode, the filter settles in a single conversion.
at sample rates ranging from 10SPS to 14.4kSPS. The programmable averaging yields output data rates
from 10SPS to 14.4kSPS.
Figure 32 shows a block diagram of the ADS1259.
The device allows unipolar or bipolar analog The ADS1259 integrates a low-drift, low-noise +2.5V
power-supply configuration (AVDD – AVSS = 5V reference. The internal reference can drive loads up
total). The analog supplies may be set to single +5V to ±10mA. The ADS1259 also operates from an
to accept unipolar (or offset-bipolar) signals or the external reference if desired. The reference input is
supplies can be set to ±2.5V to accept true bipolar buffered to reduce loading of external circuits.
signals. The operating range of the digital power
An onboard oscillator is provided as the clock source
supply (DVDD) is 2.7V to 5V.
for the device. Optionally, an external crystal can be
An internal low dropout regulator (LDO) powers the used. As a third clock option, the device can be
digital core from the DVDD supply while the device driven by an external clock source. SYNCOUT is an
I/O operates directly from DVDD. BYPASS is the output that provides a 1/8 rate clock intended to drive
LDO output and requires a 0.1μF or larger capacitor the chopping clock input of the PGA280.
to ground.
Gain and offset registers scale the digital filter output
The inherently stable, fourth-order, ΔΣ modulator to produce the final code value. On-command
measures the differential input signal [V
IN
= (AINP – calibration corrects for system offset and gain errors.
AINN)] against the differential reference [V
REF
=
An SPI-compatible serial interface provides the
(VREFP – VREFN)]. A fast responding out-of-range
control and configuration as well as the data interface
detector flags the output data if the input should
to the ADS1259. Onboard registers combined with
over-range while converting.
commands are used to control and configure the
device.
The RESET/PWDN pin is dual function. A momentary
low resets the device and, if the pin is held low,
powers down the device. The START pin, as well as
commands, controls the conversions.
Figure 32. ADS1259 Block Diagram
12 Copyright © 2009–2011, Texas Instruments Incorporated