Datasheet

SCLK
CS
(1)
DIN
DOUT
t
SCLK
t
CSSC
t
SPW
t
DIST
t
DIHD
t
SPW
t
CSDO
Hi-ZHi-Z
t
CSPW
t
DOPD
t
DOHD
NOTE:(1) canbetiedlow.CS
DRDY
DOUT
t
DRDY
t
DDO
ADS1258-EP
www.ti.com SBAS445D –MARCH 2009– REVISED MARCH 2011
PARAMETER MEASUREMENT INFORMATION
Figure 1. Serial Interface Timing
SERIAL INTERFACE TIMING CHARACTERISTICS
At T
A
= –40°C to +105°C
(1)
and DVDD = 2.7 V to 5.25 V, unless otherwise noted.
SYMBOL DESCRIPTION MIN MAX UNITS
t
SCLK
SCLK Period 2 τ
CLK
(2)
t
SPW
SCLK High or Low Pulse Width (exceeding max resets SPI interface) 0.8 4096
(3)
τ
CLK
t
CSSC
CS Low to First SCLK: Setup Time
(4)
2.5 τ
CLK
t
DIST
Valid DIN to SCLK Rising Edge: Setup Time 10 ns
t
DIHD
Valid DIN to SCLK Rising Edge: Hold Time 5 ns
t
DOPD
SCLK Falling Edge to Valid New DOUT: Propagation Delay
(5)
20 ns
t
DOHD
SCLK Falling Edge to Old DOUT Invalid: Hold Time 0 ns
t
CSDO
CS High to DOUT Invalid (tri-state) 5 τ
CLK
t
CSPW
CS Pulse Width High 2 τ
CLK
(1) Ensured by characterization only.
(2) τ
CLK
= master clock period = 1/f
CLK
.
(3) Programmable to 256 τ
CLK
.
(4) CS can be tied low.
(5) DOUT load = 20 pF || 100kΩ to DGND.
Figure 2. DRDY Update Timing
DRDY UPDATE TIMING CHARACTERISTICS
SYMBOL DESCRIPTION TYP UNITS
t
DRDY
DRDY High Pulse Width Without Data Read 1 τ
CLK
t
DDO
Valid DOUT to DRDY Falling Edge (CS = 0) 0.5 τ
CLK
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