Datasheet

ADS1258-EP
www.ti.com SBAS445D –MARCH 2009– REVISED MARCH 2011
REGISTERS
Table 12. Register Map
ADDRESS REGISTER DEFAULT
Bits A[3:0] NAME VALUE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
00h CONFIG0 0Ah 0 SPIRST MUXMOD BYPAS CLKENB CHOP STAT 0
01h CONFIG1 83h IDLMOD DLY2 DLY1 DLY0 SBCS1 SBCS0 DRATE1 DRATE0
02h MUXSCH 00h AINP3 AINP2 AINP1 AINP0 AINN3 AINN2 AINN1 AINN0
03h MUXDIF 00h DIFF7 DIFF6 DIFF5 DIFF4 DIFF3 DIFF2 DIFF1 DIFF0
04h MUXSG0 FFh AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0
05h MUXSG1 FFh AIN15 AIN14 AIN13 AIN12 AIN11 AIN10 AIN9 AIN8
06h SYSRED 00h 0 0 REF GAIN TEMP VCC 0 OFFSET
07h GPIOC FFh CIO7 CIO6 CIO5 CIO4 CIO3 CIO2 CIO1 CIO0
08h GPIOD 00h DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 DIO0
09h ID 8Bh ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
CONFIG0: CONFIGURATION REGISTER 0 (Address = 00h)
7 6 5 4 3 2 1 0
0 SPIRST MUXMOD BYPAS CLKENB CHOP STAT 0
Default = 0Ah.
Bit 7 Must be 0 (default)
Bit 6 SPIRST SPI Interface Reset Timer
This bit sets the number of f
CLK
cycles in which SCLK is inactive the SPI interface will reset. This
places a lower limit on the frequency of SCLK in which to read or write data to the device. The SPI
interface only is reset and not the device itself. When the SPI interface is reset, it is ready for a new
command.
0 = Reset when SCLK inactive for 4096f
CLK
cycles (256µs, f
CLK
= 16MHz) (default).
1 = Reset when SCLK inactive for 256f
CLK
cycles (16µs, f
CLK
= 16MHz).
Bit 5 MUXMOD
This bit sets either the Auto-Scan or Fixed-Channel mode of operation.
0 = Auto-Scan Mode (default)
In Auto-Scan mode, the input channel selections are eight differential channels (DIFF0–DIFF7) and 16
single-ended channels (AIN0–AIN15). Additionally, five internal monitor readings can be selected.
These selections are made in registers MUXDIF, MUXSG0, MUXSG1, and SYSRED. In this mode,
settings in register MUXSCH have no effect. See the Auto-Scan Mode section for more details.
1 = Fixed-Channel Mode
In Fixed-Channel mode, any of the analog input channels may be selected for the positive
measurement and the negative measurement channels. The inputs are selected in register MUXSCH.
In this mode, registers MUXDIF, MUXSG0, MUXSG1, and SYSRED have no effect. Note that it is not
possible to select the internal monitor readings in this mode.
Bit 4 BYPAS
This bit selects either the internal or external connection from the multiplexer output to the ADC input.
0 = ADC inputs use internal multiplexer connection (default).
1 = ADC inputs use external ADC inputs (ADCINP and ADCINN).
Note that the Temperature, V
CC
, Gain, and Reference internal monitor readings automatically use the
internal connection, regardless of the BYPAS setting. The Offset reading uses the setting of BYPAS.
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