Datasheet

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
CS
SCLK
DIN Command Byte Register Data
(1)
Register Data
(1)(2)
(1) One or more bytes depending on MUL bit.
(2) After the prescribed number of registers are read, then one or more additional commands can be issued in succession.
NOTE:
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
CS
SCLK
DIN Command 1 Command 2
(1)
Command 3
(1)
NOTE: (1) One or more commands can be issued in succession.
ADS1258-EP
www.ti.com SBAS445D –MARCH 2009– REVISED MARCH 2011
Register Read Command
Beginning with the eighth SCLK rising edge
(command byte completed), the MSB of the data is
To read register data, the first three bits of the
shifted in. The remaining seven SCLK rising edges
command byte to be shifted into the device are 010.
complete the write to a single register. If MUL = '1',
These bits are followed by the multiple register read
the data to the next register can be written by
bit (MUL). If MUL = '1', then multiple registers can be
supplying additional SCLKs. The operation terminates
read in sequence beyond the desired register. If
when the last register is accessed (address = 09h),
MUL = '0', only data from the addressed register can
as shown in Figure 60.
be read. The last four bits of the command word are
the beginning register address bits. During this time,
CONTROL COMMANDS
the invalid data may appear on DOUT until the
command is completed. This data should be ignored.
Pulse Convert Command
Beginning with the eighth falling edge of SCLK
(command byte completed), the MSB of the register
(See Conversion Control section)
data is output on DOUT. The remaining eight SCLK
transitions complete the read of a single register. If
Reset Command
MUL = '1', the data from the next register can be read
The Reset command resets the ADC. All registers
in sequence by supplying additional SCLKs. The
are reset to their default values. A conversion in
operation terminates when the last register is
process continues but is invalid when completed
accessed (address = 09h); see Figure 59.
(DRDY low). This conversion data should be
discarded. Note that the SPI interface may require
Register Write Command
reset for this command, or any command, to function.
To write register data, the first three bits of the
To ensure device reset under a possible locked SPI
command byte to be shifted into the device are 011.
interface condition, do one of the following: 1) toggle
These bits are followed by the multiple register read
CS high then low and send the reset command; or 2)
bit (MUL). If MUL = '1', then multiple registers can be
hold SCLK inactive for 256/f
CLK
or 4096/f
CLK
and send
written in sequence beyond the desired register. If
the reset command. The control commands are
MUL = '0', only data to the addressed register can be
illustrated in Figure 61.
written. The remaining four bits of the command word
are the beginning register address bits. During this
time, the invalid data may appear on DOUT until the
command is completed. This data should be ignored.
Figure 60. Register Write Operation
Figure 61. Control Command Operation
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