Datasheet

DRDY
DRDY
SCLK
SCLK
DRDY with SCLK
DRDY without SCLK
t
DRDYPLS
t
DRDYPLS
=
1
f
CLK
ADS1258-EP
SBAS445D –MARCH 2009– REVISED MARCH 2011 www.ti.com
Data Ready Output (DRDY)
DRDY is usually connected to an interrupt of a
controller, DSP, or connected to a controller port pin
The DRDY pin is an output that asserts low to
for polling in a software loop. Channel data can be
indicate when new channel data is available to read
read without the use of DRDY. Read the data using
(the previous conversion data is lost). DRDY returns
the register format read and check the Status Byte
high after the first falling edge of SCLK during a data
when the NEW bit = 1, which indicates new channel
read operation. If the data is not read (no SCLK
data.
pulses), DRDY remains low until new channel data is
available once again. DRDY then pulses high, then
Output Data Scaling and Over-Range
low to indicate new data is available; see Figure 53.
The ADS1258 is scaled such that the output data
code resulting from an input voltage equal to ±V
REF
has a margin of 6.6% before clipping. This
architecture allows operation of applied input signals
at or near full-scale without overloading the converter.
Specifically, the device is calibrated so that:
1LSB = V
REF
/780000h,
and the output clips when:
|V
IN
| ≥ 1.06 × V
REF
.
Table 8 summarizes the ideal output codes versus
input signals.
Figure 53. DRDY Timing
(See Figure 2 for the DRDY Pulse)
Table 8. Ideal Output Code vs Input Signal
INPUT SIGNAL V
IN
(ADCINP – ADCINN) IDEAL OUTPUT CODE
(1)
DESCRIPTION
≥ +1.06 V
REF
7FFFFFh Maximum Positive Full-Scale Before Output Clipping
+V
REF
780000h V
IN
= +V
REF
+1.06 V
REF
/(2
23
– 1) 000001h +1LSB
0 000000h Bipolar Zero
–1.06 V
REF
/(2
23
– 1) FFFFFFh –1LSB
–V
REF
87FFFFh V
IN
= –V
REF
≤ –1.06 V
REF
× (2
23
/2
23
– 1) 800000h Maximum Negative Full-Scale Before Output Clipping
(1) Excludes effects of noise, linearity, offset, and gain errors.
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