Datasheet

ADC
Multiplexer
(chopping)
AINn
AINn
MUXOUTP
MUXOUTN
ADCINP
Optional
Signal
Conditioning
ADCINN
GPIO Pin
GPIO Data (read)
GPIO Data (write)
GPIO Control
ADS1258-EP
SBAS445D –MARCH 2009– REVISED MARCH 2011 www.ti.com
EXTERNAL CHOPPING GPIO DIGITAL PORT (GPIOx)
The modulator of the ADS1258 incorporates a The ADS1258 has eight dedicated pins for
chopping front-end which removes offset errors, General-Purpose Digital I/O (GPIO). The digital I/O
providing excellent offset and offset drift performance. pins are individually configurable as either inputs or
However, offset and offset drift originating from as outputs through the GPIOC (GPIO-Configure)
external signal conditioning are not removed by the register. The GPIOD (GPIO-Data) register controls
modulator. The ADS1258 has an additional chopping the level of the pins. When reading the GPIOD
feature that removes external offset errors (CHOP = register, the data returned is the level of the pins,
1). whether they are programmed as inputs or outputs.
As inputs, a write to the GPIOD has no effect. As
With external chopping enabled, the converter takes
outputs, a write to the GPIOD sets the output value.
two readings in succession on the same channel. The
first reading is taken with one polarity and the second During Standby and Power-Down modes, the GPIO
reading is taken with the opposite polarity. The remains active. If configured as inputs, they must be
converter averages the two readings, canceling the driven (do not float). If configured as outputs, they
offset, as shown in Figure 49. With chopping enabled, continue to drive the pins. The GPIO pins are set as
the effective reading is reduced to half of the nominal inputs after power-on or after a reset. Figure 50
reading rate. shows the GPIO port structure.
Figure 49. External Chopping
Figure 50. GPIO Port Pin
Note that since the inputs are reversed under control
of the ADS1258, a delay time may be necessary to
provide time for external signal conditioning to fully
POWER-DOWN INPUT (PWDN)
settle before the second phase of the reading
The PWDN pin is used to control the power-down
sequence starts (see the Switch time Delay section).
mode of the converter. In power-down mode, all
External chopping can be used to significantly reduce
internal circuitry is deactivated including the oscillator
total offset errors (to less than 10μV) and offset drift
and the clock output. Hold PWDN low for at least two
over temperature (to less than 0.2μV/°C). Note that
f
CLK
cycles to engage power-down. The register
chopping must be disabled (CHOP = 0) to take the
settings are retained during power-down. When the
internal monitor readings.
pin is returned high, the converter requires a wake-up
time before readings can be taken, as shown in the
Power-Up Timing section. Note that in power-down
mode, the inputs of the ADS1258 must still be driven
and the device continues to drive the outputs.
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