Datasheet

ADS1258-EP
SBAS445D –MARCH 2009– REVISED MARCH 2011 www.ti.com
Table 4. Noise Performance
(1)
DATA RATE EFFECTIVE
DATA RATE FIXED-CHANNEL INPUT-REFERRED NOISE-FREE NUMBER
AUTO-SCAN MODE MODE NOISE RESOLUTION OF BITS
DRATE[1:0] (SPS) (SPS) (µV
RMS
) (Bits) (ENOB)
11 23739 125000 12 16.8 19.5
10 15123 31250 7.9 17.4 20.1
01 6168 7813 4.5 18.2 20.9
00 1831 1953 2.8 18.9 21.6
(1) V
REF
= 4.096V, f
CLK
= 16MHz, Chop = 0, Delay = 0, Inputs shorted, and 2048 sample size.
Table 5. Effective Data Rates with Switch-Time Delay (Auto-Scan Mode)
(1)
TIME DELAY TIME DELAY
DLY[2:0] (128/f
CLK
periods) (μS) DRATE[1:0] = 11 DRATE[1:0] = 10 DRATE[1:0] = 01 DRATE[1:0] = 00
000 0 0 23739 15123 6168 1831
001 1 8 19950 13491 5878 1805
010 2 16 17204 12177 5614 1779
011 4 32 13491 10191 5151 1730
100 8 64 9423 7685 4422 1639
101 16 128 5878 5151 3447 1483
110 32 256 3354 3104 2392 1247
111 48 384 2347 2222 1831 1075
(1) Time delay and data rates scale with f
CLK
. If Chop = 1, the data rates are half those shown. f
CLK
= 16MHz, Auto-Scan Mode.
Use of the switch time delay register reduces the
EXTERNAL MULTIPLEXER LOOP
effective channel data rate. Table 5 shows the actual
data rates derived from Equation 2, when using the
The external multiplexer loop consists of two
switch time delay feature.
differential multiplexer output pins and two differential
ADC input pins. The user may use external
When pulse converting, where one channel is
components (buffering/filtering, single-ended to
converted with each START pin pulse or each pulse
differential conversion, etc.), forming a signal
command, the application software may provide the
conditioning loop. For best performance, the ADC
required time delay between pulses. However, with
input should be buffered and driven differentially.
Chop = 1, the switch time delay feature may still be
necessary to allow for settling.
To bypass the external multiplexer loop, connect the
ADC input pins directly to the multiplexer output pins,
In estimating the time delay that may be required,
or select internal bypass connection (BYPASS = 0 of
Table 6 lists the time delay-to-time constant ratio (t/τ)
CONFIG0). Note that the multiplexer output pins are
and the corresponding final settled data in % and
active regardless of the bypass setting.
number of bits.
SWITCH TIME DELAY
Table 6. Settling Time
When using the ADS1258 in the Auto-Scan mode,
FINAL SETTLING FINAL SETTLING
where the converter automatically switches from one
t/τ
(1)
(%) (Bits)
channel to the next, the settling time of the external
1 63 2
signal conditioning circuit becomes important. If the
3 95 5
channel does not fully settle after the multiplexer
5 99.3 7
channel is switched, the data may not be correct. The
7 99.9 10
ADS1258 provides a switch time delay feature which
automatically provides a delay after channel switching
10 99.995 14
to allow the channel to settle before taking a reading.
15 99.9999 20
The amount of time delay required depends primarily
17 99.999994 24
on the settling time of the external signal conditioning.
Additional consideration may be needed to account
for the settling of the input source arising from the
transient generated from channel switching.
(1) Multiple time constants can be approximated by:
(τ
1
2
+ τ
2
2
+…).
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