Datasheet

DRDY 1 2
Step Input
Data Not Settled Settled Data
DRDY 1 2 6
Step Input
Data Not Settled Settled Data
0
−
20
−
40
−
60
−
80
−
100
−
120
−
140
Frequency (MHz)
Gain (dB)
4 80 12 16
DRATE[1:0] = 11
125kSPS
Fixed−Channel Mode
ENOB +
ln
ǒ
FSRńRMS Noise
Ǔ
ln(2)
ADS1258-EP
www.ti.com SBAS445D –MARCH 2009– REVISED MARCH 2011
ALIASING input. For most modes of operation, the analog input
must be stable for one complete conversion cycle to
The digital filter low-pass characteristic repeats at
provide settled data. In Fixed-Channel mode
multiples of the modulator rate of f
CLK
/2. Figure 45
(DRATE[1:0] = 11), the input must be stable for five
shows the response plotted out to 16MHz at the data
complete conversion cycles.
rate of 125 kSPS (Fixed-Channel mode). Notice how
the responses near DC, 8 MHz, and 16 MHz are the
same. The digital filter attenuates high-frequency
noise on the ADS1258 inputs up to the frequency
where the response repeats. However, noise or
frequency components present on the analog input
where the response repeats alias into the passband.
For most applications, an anti-alias filter is
recommended to remove the noise. A simple
first-order input filter with a pole at 200kHz
provides –34dB rejection at the first image frequency.
Figure 46. Asynchronous Step-Input Settling
Time (DRATE[1:0] = 10, 01, 00)
Figure 47. Asynchronous Step-Input Settling
Time (Fixed-Channel Mode, DRATE[1:0] = 11)
NOISE PERFORMANCE
Figure 45. Frequency Response Out to 16MHz
The ADS1258 offers outstanding noise performance
that can be optimized by adjusting the data rate. As
the averaging is increased by reducing the data rate,
Referring to Figure 43 and Figure 44, frequencies
noise drops correspondingly. See Table 4 for
present on the analog input above the Nyquist rate
Input-Referred Noise, Noise-Free Resolution, and
(sample rate/2) are first attenuated by the digital filter
Effective Number of Bits (ENOB). The noise
and then alias into the passband.
performance of low-level signals can be improved
substantially by using external gain. Note that when
SETTLING TIME
Chop = 1, the data rate is reduced by 2x and the
The design of the ADS1258 provides fully-settled
noise is reduced by 1.4x.
data when scanning through the input channels in
ENOB is defined in Equation 5:
Auto-Scan mode. The DRDY flag asserts low when
the data for each channel is ready. It may be
necessary to use the automatic switch time delay
(5)
feature to provide time for settling of the external
where FSR is the full-scale range.
buffer and associated components after channel
switching. When the converter is started (START pin
The data for the Noise-Free Resolution (bits) is
transitions high or Start Command) with stable inputs,
calculated in the same way as ENOB, except
the first converter output is fully settled. When
peak-to-peak noise is used.
applying asynchronous step inputs, the settling time
is somewhat different. The step-input settling time
As seen in the illustration of Noise vs V
REF
diagrams (Figure 46 and Figure 47) show the
(Figure 10), the converter noise is relatively constant
converter step response with an asynchronous step
versus the reference voltage. Optimum
signal-to-noise ratio of the converter is achieved by
using higher reference voltages (V
REF MAX
= AVDD –
AVSS).
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