Datasheet

f
CLK
128
(
4
11b*DR
) 4.265625 ) TD
)
2
CHOP
f
CLK
128
(
4
11b*DR
) CHOP
(
4.265625 ) TD
))
2
CHOP
Analog
Modulator
sinc
5
Filter
Programmable
Averager
Data Rate = f
CLK
/128Modulator Rate = f
CLK
/2
Num_Ave
Data Rate
(1)
= f
CLK
/(128
×
Num_Ave)
NOTE: (1) Data rate for Fixed−Channel Mode, Chop = 0, Delay = 0.
ADS1258-EP
www.ti.com SBAS445D –MARCH 2009– REVISED MARCH 2011
Make sure to use a clock source clean from jitter or rate—filter more for higher resolution, filter less for
interference. Ringing or under/overshoot should be higher data rate. The filter is comprised of two
avoided. A 50 Ω resistor in series with the CLKIO pin sections, a fixed filter followed by a programmable
(placed close to the source) can often help. filter. Figure 42 shows the block diagram of the filter.
Data is supplied to the filter from the analog
modulator at a rate of f
CLK
/2. The fixed filter is a
ADC
fifth-order sinc filter with a decimation value of 64 that
The ADC block of the ADS1258 is composed of two
outputs data at a rate of f
CLK
/128. The second stage
blocks: a modulator and a digital filter.
of the filter is a programmable averager (first-order
sinc filter) with the number of averages set by the
Modulator
DRATE[1:0] bits.
The modulator converts the analog input voltage into
The data rate depends upon the system clock
a Pulse Code Modulated (PCM) data stream. When
frequency (f
CLK
) and the converter configuration. The
the level of differential analog input (ADCINP –
data rate can be computed by Equation 2 or
ADCINN) is near the level of the reference voltage,
Equation 3:
the '1' density of the PCM data stream is at its
Data Rate (Auto-Scan):
highest. When the level of the differential analog input
is near zero, the PCM '0' and '1' densities are nearly
equal. The fourth-order modulator shifts the
(2)
quantization noise to a high frequency (out of the
passband) where the digital filter can easily remove it.
Data Rate (Fixed-Channel Mode):
The modulator continuously chops the input, resulting
in excellent offset and offset drift performance. It is
(3)
important to note that offset or offset drift originating
Where:
from the external circuitry is not removed by the
DR = DRATE[1:0] register bits (binary).
modulator chopping. These errors can be effectively
removed by using the external chopping feature of
CHOP = Chop register bit.
the ADS1258 (see the External Chopping section).
TD = time delay value given in Table 5 from the
DLY[2:0] register bits (128/f
CLK
periods).
Digital Filter
The programmable low-pass digital filter receives the
modulator output and produces a high-resolution
digital output. By adjusting the amount of filtering,
tradeoffs can be made between resolution and data
Figure 42. Block Diagram of Digital Filter
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