Datasheet

50
Ω
32.768kHz
(1)
4.7pF 4.7pF
22nF
CLKSEL XTAL1 XTAL2 PLLCAP
AVSS
CLKIO
Clock Output
(15.729MHz)
0V to −2.5V
NOTE: (1) Parallel resonant type, C
L
= 12.5pF, ESR = 35k
Ω
(max).
Place the crystal and load capacitors as close as possible to the device pins.
Oscillator
andPLL
MUX
CLKENB
Bit
InternalMasterClock(f )
CLK
CLKSEL
CLKIO
XTAL1 XTAL2 PLL
50
Ω
CLKSEL XTAL1 XTAL2 PLLCAP
DVDD
CLKIO
Clock Input
(16MHz)
2.7V
to 5V
No Connection
ADS1258-EP
SBAS445D –MARCH 2009– REVISED MARCH 2011 www.ti.com
MASTER CLOCK (f
CLK
)
The ADS1258 oversamples the analog input at a high
rate. This requires a high-frequency master clock to
be supplied to the converter. As shown in Figure 39,
the clock comes from either an internal oscillator (with
external crystal), or an external clock source.
Figure 40. Crystal Oscillator Connection
Table 1. System Clock Source
CLKSEL CLKENB
PIN CLOCK SOURCE BIT CLKIO FUNCTION
32.768 kHz Disabled
0 0
Crystal Oscillator (internally grounded)
Figure 39. Clock Generation Block Diagram
32.768 kHz
0 1 Output (15.729 MHz)
Crystal Oscillator
The CLKSEL pin determines the source of the
1 External Clock Input X Input (16 MHz)
system clock, as shown in Table 1. The CLKIO pin
functions as an input or as an output. When the
Table 2. Approved Crystal Vendors
CLKSEL pin is set to '1', CLKIO is configured as an
input to receive the master clock. When the CLKSEL
VENDOR CRYSTAL PRODUCT
pin is set to '0', the crystal oscillator generates the
C-001R
clock. The CLKIO pin can then be configured to
Epson MC-306 32.7680K-A0
output the master clock. When the clock output is not
FC-135 32.7680KA-A0
needed, it can be disabled to reduce device power
ECS ECS-.327-12.5-17-TR
consumption.
Crystal Oscillator
External Clock Input
An on-chip oscillator and Phase-Locked Loop (PLL)
When using an external clock to operate the device,
together with an external crystal can be used to
apply the master clock to the CLKIO pin. For this
generate the system clock. For this mode, tie the
mode, the CLKSEL pin is tied high. CLKIO then
CLKSEL pin low. A 22nF PLL filter capacitor,
becomes an input, as shown in Figure 41.
connected from the PLLCAP pin to the AVSS pin, is
required. The internal clock of the PLL can be output
to the CLKIO to drive other converters or controllers.
If not used, disable the clock output to reduce device
power consumption; see Table 1 for settings. The
clock output is enabled by a register bit setting
(default is ON). Figure 40 shows the oscillator
connections. Place these components as close to the
pins as possible to avoid interference and coupling.
Do not connect XTAL1 or XTAL2 to any other logic.
The oscillator start-up time may vary, depending on
the crystal and ambient temperature. The user should
Figure 41. External Clock Connection
verify the oscillator start-up time.
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