AD S1 258 ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com 16-CHANNEL, 24-BIT ANALOG-TO-DIGITAL CONVERTER Check for Samples: ADS1258-EP FEATURES 1 • • • • • • • • • • 23 • • • • • • • • 24 Bits, No Missing Codes Fixed-Channel or Automatic Channel Scan Fixed-Channel Data Rate: 125 kSPS Auto-Scan Data Rate: 23.7 kSPS/Channel Single-Conversion Settled Data 16 Single-Ended or 8 Differential Inputs Unipolar (5 V) or Bipolar (±2.5 V) Operation Low Noise: 2.8 μVRMS at 1.8 kSPS 0.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com AVDD DVDD VREF Internal Monitoring GPIO[7:0] ADS1258 GPIO Digital Filter SPI Interface CS DRDY SCLK DIN DOUT Oscillator Control START RESET PWDN 1 16:1 Analog Input MUX … Analog Inputs 24−Bit ADC 16 AINCOM AVSS MUX OUT ADC IN Extclk In/Out 32.768kHz DGND This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com ELECTRICAL CHARACTERISTICS All specifications at TA = –55°C to 125°C, AVDD = 2.5 V, AVSS = –2.5 V, DVDD = 3.3 V, fCLK = 16 MHz (external clock) or fCLK = 15.729 MHz (internal clock), OPA227 buffer between MUX outputs and ADC inputs, VREF = 4.096 V, and VREFN = –2.5 V, unless otherwise noted.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = –55°C to 125°C, AVDD = 2.5 V, AVSS = –2.5 V, DVDD = 3.3 V, fCLK = 16 MHz (external clock) or fCLK = 15.729 MHz (internal clock), OPA227 buffer between MUX outputs and ADC inputs, VREF = 4.096 V, and VREFN = –2.5 V, unless otherwise noted. PARAMETER CONDITIONS MIN TYP (1) MAX UNIT Digital Input/Output Logic Levels VIH 0.7 DVDD DVDD V VIL DGND 0.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION CS(1) tCSPW tCSSC tSCLK tSPW SCLK tSPW tDIST DIN tDIHD Hi-Z tDOPD Hi-Z DOUT tCSDO tDOHD NOTE: (1) CS can be tied low. Figure 1. Serial Interface Timing SERIAL INTERFACE TIMING CHARACTERISTICS At TA= –40°C to +105°C (1) (2) (3) (4) (5) (1) and DVDD = 2.7 V to 5.25 V, unless otherwise noted.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com ADS1258 48/RTC Package Operating Life Derating Chart 10 00 Wirebond Voiding Fail Mode Years of Estimaed Life 1 00 Electromigration Fail Mode 10 1 80 90 100 110 120 130 140 150 16 0 Continuous TJ (°C) Figure 3. Notes: 1. See datasheet for absolute maximum and minimum recommended operating conditions. 2. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life).
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise noted.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise noted.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise noted.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise noted.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise noted.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com OVERVIEW VIN = (ADCINP – ADCINN), against the differential reference input, VREF = (VREFP – VREFN). The digital filter receives the modulator signal and provides a low-noise digital output. The ADC channel block controls the multiplexer Auto-Scan feature. Channel Auto-Scan occurs at a maximum rate of 23.7kSPS. Slower scan rates can be used with corresponding increases in resolution.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com MULTIPLEXER INPUTS A simplified diagram of the input multiplexer is illustrated in Figure 36. The multiplexer connects one of 16 single-ended external inputs, one of eight differential external inputs, or one of the on-chip internal variables to the ADC inputs. The output of the channel multiplexer can be routed to external pins and then to the input of the ADC. This flexibility allows for use of external signal conditioning.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com VREFP VREFN Multiplexer Reference/Gain Monitor AIN0 AIN1 AIN2 Temperature Sensor Monitor AVDD AIN3 1x AIN4 2x AIN5 8x 1x AIN6 AVSS AIN7 Supply Monitor AIN8 AVDD AVSS AIN9 AIN10 AIN11 NOTE: ESD diodes not shown. Internal Reference AIN12 AVSS AIN13 AIN14 ADC AIN15 AINCOM (AVDD − AVSS)/2 ADCINN ADCINP Offset Monitor MUXOUTP Sensor Bias MUXOUTN AVSS AVDD Figure 36.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com ADC INPUTS The ADS1258 ADC inputs (ADCINP, ADCINN) measure the input signal using internal capacitors that are continuously charged and discharged. The left side of Figure 38 shows a simplified schematic of the ADC input circuitry; the right side of Figure 38 shows the input circuitry with the capacitors and switches replaced by an equivalent circuit. Figure 37 shows the ON/OFF timings of the switches shown in Figure 38.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com MASTER CLOCK (fCLK) The ADS1258 oversamples the analog input at a high rate. This requires a high-frequency master clock to be supplied to the converter. As shown in Figure 39, the clock comes from either an internal oscillator (with external crystal), or an external clock source. 50Ω CLKSEL XTAL1 CLKENB Bit XTAL2 CLKIO Clock Output (15.729MHz) AVSS 0V to −2.5V PLLCAP 32.768kHz(1) 22nF 4.7pF 4.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com Make sure to use a clock source clean from jitter or interference. Ringing or under/overshoot should be avoided. A 50 Ω resistor in series with the CLKIO pin (placed close to the source) can often help. ADC The ADC block of the ADS1258 is composed of two blocks: a modulator and a digital filter. Modulator The modulator converts the analog input voltage into a Pulse Code Modulated (PCM) data stream.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com Table 3 shows a listing of the averaging and data rates for each of the four DRATE[1:0] register settings for the Auto-Scan and Fixed-Channel modes, with CHOP, DLY = 0. Note that the data rate scales directly with fCLK. For example, reducing fCLK by 2x reduces the maximum data rate by 2x. Figure 44 shows the response with averaging set to 4 (DRATE[1:0] = 10).
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com ALIASING The digital filter low-pass characteristic repeats at multiples of the modulator rate of fCLK/2. Figure 45 shows the response plotted out to 16MHz at the data rate of 125 kSPS (Fixed-Channel mode). Notice how the responses near DC, 8 MHz, and 16 MHz are the same. The digital filter attenuates high-frequency noise on the ADS1258 inputs up to the frequency where the response repeats.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com Table 4. Noise Performance (1) (1) DRATE[1:0] DATA RATE AUTO-SCAN MODE (SPS) DATA RATE FIXED-CHANNEL MODE (SPS) INPUT-REFERRED NOISE (µVRMS) NOISE-FREE RESOLUTION (Bits) EFFECTIVE NUMBER OF BITS (ENOB) 11 23739 10 15123 125000 12 16.8 19.5 31250 7.9 17.4 20.1 01 00 6168 7813 4.5 18.2 20.9 1831 1953 2.8 18.9 21.6 VREF = 4.096V, fCLK = 16MHz, Chop = 0, Delay = 0, Inputs shorted, and 2048 sample size. Table 5.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com SENSOR BIAS An integrated current source provides a means to bias an external sensor (for example, a diode junction); or, it verifies the integrity of a sensor or sensor connection. When the sensor fails to an open condition, the current sources drive the inputs of the converter to positive full-scale. The biasing is in the form of differential currents (programmable 1.5μA or 24μA), connected to the output of the multiplexer.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com EXTERNAL CHOPPING GPIO DIGITAL PORT (GPIOx) The modulator of the ADS1258 incorporates a chopping front-end which removes offset errors, providing excellent offset and offset drift performance. However, offset and offset drift originating from external signal conditioning are not removed by the modulator. The ADS1258 has an additional chopping feature that removes external offset errors (CHOP = 1).
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com Table 7. Wake-Up Times POWER-UP TIMING When powering up the device or taking the PWDN pin high to wake the device, a wake-up time is required before readings can be taken. When using the internal oscillator, the wake-up time is composed of the oscillator start-up time and the PLL lock time, and if the supplies are also being powered, there is a reset interval time of 218 fCLK cycles.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com Data Ready Output (DRDY) The DRDY pin is an output that asserts low to indicate when new channel data is available to read (the previous conversion data is lost). DRDY returns high after the first falling edge of SCLK during a data read operation. If the data is not read (no SCLK pulses), DRDY remains low until new channel data is available once again. DRDY then pulses high, then low to indicate new data is available; see Figure 53.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com INTERNAL SYSTEM READINGS Analog Power-Supply Reading (VCC) The analog power-supply voltage of the ADS1258 can be monitored by reading the VCC register. The supply voltage is routed internal to the ADS1258 and is measured and scaled using an internal reference. The supply readback channel outputs the difference between AVDD and AVSS (AVDD – AVSS), for both single and dual configurations.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com CONVERSION CONTROL Pulse Convert Command The conversions of the ADS1258 are controlled by the START pin. Conversions begin when the START pin is taken high and conversions are stopped when the START pin is taken low. For continuous conversions, tie the START pin high. The START pin can also be tied low and the conversions controlled by the PULSE convert command. The PULSE convert command converts one channel (only) for each command sent.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com GPIO Linked START Pin Control OPERATING MODES The START pin can be contolled directly by software by connecting externally a GPIO port pin to the START pin. (Note that an external pull-down resistor is recommended to keep the GPIO from floating until the GPIO is configured as an output).
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com Auto-Scan Mode The ADS1258 provides 16 analog inputs, which can be configured in combinations of eight differential inputs or 16 single-ended inputs, and provides an additional five internal system measurements. Taken together, the device allows a total of 29 possible channel combinations.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com write operations in progress will terminate and the SPI interface resets. This timeout feature can be used to recover lost communication when a serial interface transmission is interrupted or inadvertently glitched. may be read at any time without concern to DRDY. The NEW bit of the STATUS byte indicates that the data register has been refreshed with new converter data since the last read operation.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com COMMAND DESCRIPTION SCLK falling edge (command byte completed), the MSB of the channel data is restarted on DOUT. The user clocks the data on the following rising edge of SCLK. A total of 40 SCLK transitions complete the data read operation. Unlike the direct read mode, the channel data can be read during a DRDY transition without data corruption.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com Register Read Command Beginning with the eighth SCLK rising edge (command byte completed), the MSB of the data is shifted in. The remaining seven SCLK rising edges complete the write to a single register. If MUL = '1', the data to the next register can be written by supplying additional SCLKs. The operation terminates when the last register is accessed (address = 09h), as shown in Figure 60.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com CHANNEL DATA The data read operation outputs either four bytes (one byte for status and three bytes for data), or three bytes for data only. The selection of 4-byte or 3-byte data read is set by the bit STAT in register CONFIG0 (see Table 13, Status Byte, for options). In the 4-byte read, the first byte is the status byte and the following three bytes are the data bytes. The MSB (Data23) of the data is shifted out first. Table 10.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com BITS DATA[23:0] OF DATA BYTES The ADC output data are 24 bits wide (DATA[23:0]). DATA23 is the most significant bit (MSB) and DATA0 is the least significant bit (LSB). The data is coded in binary twos complement format. Table 11.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com COMMAND AND REGISTER DEFINITIONS Commands are used to read channel data, access the configuration registers, and control the conversion process. If the command is a register read or write operation, one or more data bytes follow the command byte. If bit MUL = 1 in the command byte, then multiple registers can be read or written in one command operation (see the MUL bit).
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com REGISTERS Table 12.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com Bit 3 CLKENB This bit enables the clock output on pin CLKIO. The clock output originates from the device crystal oscillator and PLL circuit. 0 = Clock output on CLKIO disabled. 1 = Clock output on CLKIO enabled (default). Note: If the CLKSEL pin is set to '1', the CLKIO pin is a clock input only. In this case, setting this bit has no effect. Bit 2 CHOP This bit enables the chopping feature on the external multiplexer loop.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com CONFIG1: CONFIGURATION REGISTER 1 (Address = 01h) 7 6 5 4 3 2 1 0 IDLMOD DLY2 DLY1 DLY0 SBCS1 SBCS0 DRATE1 DRATE0 Default = 83h. Bit 7 IDLMOD This bit selects the Idle mode when the device is not converting, Standby or Sleep. The Sleep mode offers lower power consumption but has a longer wake-up time to re-enter the run mode; see the Idle Modes section.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com MUXSCH: MULTIPLEXER FIXED-CHANNEL REGISTER (Address = 02h) 7 6 5 4 3 2 1 0 AINP3 AINP2 AINP1 AINP0 AINN3 AINN2 AINN1 AINN0 Default = 00h. This register selects the input channels of the multiplexer to be used for the Fixed-Channel mode. The MUXMOD bit in register CONFIG0 must be set to '1'.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com GPIOC: GPIO CONFIGURATION REGISTER (Address = 07h) 7 6 5 4 3 2 1 0 CIO7 CIO6 CIO5 CIO4 CIO3 CIO2 CIO1 CIO0 Default = FFh. This register configures the GPIO pins as inputs or as outputs. Note that the default configurations of the port pins are inputs and as such they should not be left floating. See the GPIO Digital Port section. 0 = GPIO is an output; 1 = GPIO is an input (default).
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com APPLICATIONS HARDWARE CONSIDERATIONS The following summarizes the design and layout considerations when using the ADS1258: a. Power Supplies: The converter accepts a single +5V supply (AVDD = 5 V and AVSS = AGND) or dual, bipolar supplies (typically AVDD = 2.5 V, AVSS = –2.5 V). Dual supply operation accommodates true bipolar input signals, within a ±2.5-V range.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com f. Clock Source: The ADS1258 requires a clock signal for operation. The clock can originate from either the crystal oscillator or from an external clock source. The internal oscillator uses a PLL circuit and an external 32.768-kHz crystal to generate a 15.7-MHz master clock. The PLL requires a 22-nF capacitor from the PLLCAP pin to AVSS.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com 4. Configure the Registers: The registers are configured by writing to them either sequentially or as a group. The user may configure the software in either mode. Any write to the Auto-Scan channel-select registers resets the channel pointer to the channel of highest priority. 5. Verify Register Data: The register data may be read back for verification of device communications. 6.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com DIGITAL INTERFACE CONNECTIONS The ADS1258 SPI-compatible interface easily connects to a wide variety of microcontrollers and DSPs. Figure 64 shows the basic connection to TI's MSP430 family of low-power microcontrollers. Figure 65 shows the connection to microcontrollers with an SPI interface such as the 68HC11 family, or TI's MSC12xx family.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com ANALOG INPUT CONNECTIONS When using Auto-Scan mode to sequence through the channels, the switch time delay feature (programmable by registers) can be used to provide additional settling time of the external components. Figure 68 shows the ADS1258 interfacing to high-level ±10V inputs, commonly used in industrial environments.
ADS1258-EP SBAS445D – MARCH 2009 – REVISED MARCH 2011 www.ti.com +5V RFI 0.1mF 10mF + 2kW RFI AVSS AIN0 AVDD 2kW RFI REFP AIN1 ¼ ¼ ADS1258 0.1mF +5V ADCINN AINCOM RFI ADCINP AIN15 MUXOUTP 2kW RFI 10mF REFN AIN14 MUXOUTN ¼ 2kW RFI + 2.2nF 47W OPA365 R2 10kW NOTE: G = 1 + 2R2/R1. 0.1mF supply bypass capacitor not shown. R1 2.2kW R2 10kW 47W OPA365 Figure 69.
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PACKAGE OPTION ADDENDUM www.ti.com (3) 16-Mar-2011 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS1258IPHPREP Package Package Pins Type Drawing HTQFP PHP 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 9.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.6 1.5 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1258IPHPREP HTQFP PHP 48 1000 367.0 367.0 38.
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