Datasheet
ADS1255
ADS1256
SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013
www.ti.com
6
PARAMETER MEASUREMENT INFORMATION
SCLK
CS
DIN
DOUT
t
1
t
3
t
2H
t
4
t
5
t
2L
t
6
t
9
t
8
t
7
t
11
t
10
Figure 1. Serial Interface Timing
TIMING CHARACTERISTICS FOR FIGURE 1
SYMBOL DESCRIPTION MIN MAX UNIT
t
SCLK period
4 τ
CLKIN
(1)
t
1
SCLK period
10 τ
DATA
(2)
t
SCLK pulse width: high
200 ns
t
2H
SCLK pulse width: high
9 τ
DATA
t
2L
SCLK pulse width: low
200 ns
t
3
CS low to first SCLK: setup time
(3)
0 ns
t
4
Valid DIN to SCLK falling edge: setup time
50 ns
t
5
Valid DIN to SCLK falling edge: hold time
50 ns
t
6
Delay from last SCLK edge for DIN to first SCLK rising edge for DOUT: RDATA, RDATAC,
RREG Commands
50 τ
CLKIN
t
7
SCLK rising edge to valid new DOUT: propagation delay
(4)
50 ns
t
8
SCLK rising edge to DOUT invalid: hold time
0 ns
t
9
Last SCLK falling edge to DOUT high impedance
NOTE: DOUT goes high impedance immediately when CS goes high
6 10 τ
CLKIN
t
10
CS low after final SCLK falling edge
8 τ
CLKIN
RREG, WREG, RDATA
4 τ
CLKIN
Final SCLK falling edge of command to first SCLK
RDATAC, SYNC
24 τ
CLKIN
t
11
Fi
n
al SCLK falli
ng
e
d
ge
o
f
comm
a
n
d t
o
fi
rs
t SCLK
rising edge of next command.
RDATAC, RESET, STANDBY,
SELFOCAL, SYSOCAL, SELFGCAL,
SYSGCAL, SELFCAL
Wait for DRDY to go low
(1)
τ
CLKIN
= master clock period = 1/f
CLKIN
.
(2)
τ
DATA
= output data period 1/f
DATA
.
(3)
CS can be tied low.
(4)
DOUT load = 20pF ⎥⎥ 100kΩ to DGND.