Datasheet
ADS1255
ADS1256
SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013
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30
REGISTER MAP
The operation of the ADS1255/6 is controlled through a set of registers. Collectively, the registers contain all the information
needed to configure the part, such as data rate, multiplexer settings, PGA setting, calibration, etc., and are listed in
Table 23.
Table 23. Register Map
ADDRESS REGISTER
RESET
VALUE
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
00h STATUS x1
H
ID3 ID2 ID1 ID0 ORDER ACAL BUFEN DRDY
01h MUX 01
H
PSEL3 PSEL2 PSEL1 PSEL0 NSEL3 NSEL2 NSEL1 NSEL0
02h ADCON 20
H
0 CLK1 CLK0 SDCS1 SDCS0 PGA2 PGA1 PGA0
03h DRATE F0
H
DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0
04h IO E0
H
DIR3 DIR2 DIR1 DIR0 DIO3 DIO2 DIO1 DIO0
05h OFC0 xx
H
OFC07 OFC06 OFC05 OFC04 OFC03 OFC02 OFC01 OFC00
06h OFC1 xx
H
OFC15 OFC14 OFC13 OFC12 OFC11 OFC10 OFC09 OFC08
07h OFC2 xx
H
OFC23 OFC22 OFC21 OFC20 OFC19 OFC18 OFC17 OFC16
08h FSC0 xx
H
FSC07 FSC06 FSC05 FSC04 FSC03 FSC02 FSC01 FSC00
09h FSC1 xx
H
FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC09 FSC08
0Ah FSC2 xx
H
FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16
STATUS : STATUS REGISTER (ADDRESS 00h)
Reset Value = x1h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
ID ID ID ID ORDER ACAL BUFEN DRDY
Bits 7-4 ID3, ID2, ID1, ID0 Factory Programmed Identification Bits (Read Only)
Bit 3 ORDER: Data Output Bit Order
0 = Most Significant Bit First (default)
1 = Least Significant Bit First
Input data is always shifted in most significant byte and bit first. Output data is always shifted out most significant
byte first. The ORDER bit only controls the bit order of the output data within the byte.
Bit 2 ACAL: Auto-Calibration
0 = Auto-Calibration Disabled (default)
1 = Auto-Calibration Enabled
When Auto-Calibration is enabled, self-calibration begins at the completion of the WREG command that changes
the PGA (bits 0-2 of ADCON register), DR (bits 7-0 in the DRATE register) or BUFEN (bit 1 in the STATUS register)
values.
Bit 1 BUFEN: Analog Input Buffer Enable
0 = Buffer Disabled (default)
1 = Buffer Enabled
Bit 0 DRDY
: Data Ready (Read Only)
This bit duplicates the state of the DRDY
pin.