Datasheet

ADS1255
ADS1256
SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013
www.ti.com
20
0
−
20
−
40
−
60
−
80
−
100
−
120
−
140
Gain (dB)
0 1.92 3.84 5.76 7.68
Frequency (MHz)
f
DATA
=30kSPS
f
CLKIN
=7.68MHz
Figure 16. Frequency Response Out to 7.68MHz
for Data Rate = 30kSPS
0
−
20
−
40
−
60
−
80
−
100
−
120
−
140
Gain (dB)
0 1.92 3.84 5.76 7.68
Frequency (MHz)
f
DATA
=2.5SPS
f
CLKIN
= 7.68MHz
Figure 17. Frequency Response Out to 7.68MHz
for Data Rate = 2.5SPS
SETTLING TIME
The ADS1255/6 features a digital filter optimized for fast
settling. The settling time (time required for a step change
on the analog inputs to propagate through the filter) for the
different data rates is shown in Table 13. The following
sections highlight the single-cycle settling ability of the
filter and show various ways to control the conversion
process.
Table 13. Settling Time vs Data Rate
DATA RATE
(SPS)
SETTLING TIME (t
18
)
(ms)
30,000 0.21
15,000 0.25
7500 0.31
3750 0.44
2000 0.68
1000 1.18
500 2.18
100 10.18
60 16.84
50 20.18
30 33.51
25 40.18
15 66.84
10 100.18
5 200.18
2.5 400.18
NOTE: f
CLKIN
= 7.68MHz.
NOTE: One−shot mode requires a small additional delay to power
up the device from standby.
Settling Time Using Synchronization
The SYNC/PDWN pin allows direct control of conversion
timing. Simply issue a Sync command or strobe the
SYNC
/PDWN pin after changing the analog inputs (see
the Synchronization section for more information). The
conversion begins when SYNC/PDWN is taken high,
stopping the current conversion and restarting the digital
filter. As soon as SYNC
/PDWN goes low, the DRDY
output goes high and remains high during the conversion.
After the settling time (τ
18
), DRDY goes low, indicating that
data is available. The ADS1255/6 settles in a single
cycle—there is no need to ignore or discard data after
synchronization. Figure 18 shows the data retrieval
sequence following synchronization.