Datasheet
ADS1255
ADS1256
SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013
www.ti.com
16
PROGRAMMABLE GAIN AMPLIFIER (PGA)
The ADS1255/6 is a very high resolution converter. To
further complement its performance, the low-noise PGA
provides even more resolution when measuring smaller
input signals. For the best resolution, set the PGA to the
highest possible setting. This will depend on the largest
input signal to be measured. The ADS1255/6 full-scale
input voltage equals ±2V
REF
/PGA. Table 8 shows the
full-scale input voltage for the different PGA settings for
V
REF
= 2.5V. For example, if the largest signal to be
measured is 1.0V, the optimum PGA setting would be 4,
which gives a full-scale input voltage of 1.25V. Higher
PGAs cannot be used since they cannot handle a 1.0V
input signal.
Table 8. Full-Scale Input Voltage vs
PGA Setting
PGA SETTING
FULL-SCALE INPUT VOLTAGE V
IN
(1)
(V
REF
= 2.5V)
1 ±5V
2 ±2.5V
4 ±1.25V
8 ±0.625V
16 ±312.5mV
32 ±156.25mV
64 ±78.125mV
(1)
The input voltage (V
IN
) is the difference between the positive and
negative inputs. Make sure neither input violates the absolute
input voltage with respect to ground, as listed in the Electrical
Characteristics.
The PGA is controlled by the ADCON register.
Recalibrating the A/D converter after changing the PGA
setting is recommended. The time required for
self-calibration is dependent on the PGA setting. See the
Calibration section for more details. The analog current
and input impedance (when the buffer is disabled) vary as
a function of PGA setting.
MODULATOR INPUT CIRCUITRY
The ADS1255/6 modulator measures the input signal
using internal capacitors that are continuously charged
and discharged. Figure 9 shows a simplified schematic of
the ADS1255/6 input circuitry with the input buffer
disabled. Figure 10 shows the on/off timings of the
switches of Figure 9. S1 switches close during the input
sampling phase. With S1 closed, C
A1
charges to AIN
P
, C
A2
charges to AIN
N
, and C
B
charges to (AIN
P
– AIN
N
). For the
discharge phase, S1 opens first and then S2 closes. C
A1
and C
A2
discharge to approximately AVDD/2 and C
B
discharges to 0V. This two-phase sample/discharge cycle
repeats with a period of τ
SAMPLE
. This time is a function of
the PGA setting as shown in Table 9 along with the values
of the capacitor C
A1
= C
A2
= C
A
and C
B
.
AVDD/2
AVDD/2
AIN
P
AIN
N
Input
Multiplexer
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AINCOM
ADS1256 Only
S2
S1
S1
S2
C
A1
C
B
C
A2
Figure 9. Simplified Input Structure
with Buffer Off
ON
OFF
ON
S
1
S
2
OFF
τ
SAMPLE
Figure 10. S1 and S2 Switch Timing for Figure 9
Table 9. Input Sampling Time, τ
SAMPLE
, and
C
A
and C
B
vs PGA
PGA
SETTING
τ
SAMPLE
(1)
C
A
C
B
1 f
CLKIN
/4 (521ns) 2.1pF 2.4pF
2 f
CLKIN
/4 (521ns) 4.2pF 4.9pF
4 f
CLKIN
/4 (521ns) 8.3pF 9.7pF
8 f
CLKIN
/4 (521ns) 17pF 19pF
16 f
CLKIN
/4 (521ns) 33pF 39pF
32 f
CLKIN
/2 (260ns) 33pF 39pF
64 f
CLKIN
/2 (260ns) 33pF 39pF
(1)
τ
SAMPLE
for f
CLKIN
= 7.68MHz.