Datasheet

ADS1253
SBAS199B
15
www.ti.com
is at 0V and which is at 4.096V. The digital-output result,
however, is quite different. The analog-input differential volt-
age is given by the following equation:
+V
IN
– (–V
IN
)
A positive digital output is produced whenever the analog-
input differential voltage is positive, whereas a negative
digital output is produced whenever the differential is nega-
tive. For example, a positive full-scale output is produced
when the converter is configured with a 4.096V reference,
and the analog-input differential is 4.096V. The negative full-
scale output is produced when the differential voltage is
–4.096V. In each case, the actual input voltages must remain
within the –0.3V to +V
DD
range.
Actual Analog-Input Voltage—the voltage at any one ana-
log input relative to GND.
Full-Scale Range (FSR)—as with most A/D converters, the
full-scale range of the ADS1253 is defined as the input that
produces the positive full-scale digital output minus the input
that produces the negative full-scale digital output. For ex-
ample, when the converter is configured with a 4.096V
reference, the differential full-scale range is:
[4.096V (positive full-scale) – (–4.096V) (negative full-scale)] = 8.192V
Least Significant Bit (LSB) Weight—this is the theoretical
amount of voltage that the differential voltage at the analog
input would have to change in order to observe a change in the
output data of one least significant bit. It is computed as follows:
LSBWeight
Full ScaleRange V
N
REF
N
=
−
=
21
2
21–
•
–
where N is the number of bits in the digital output.
Conversion Cycle—as used here, a conversion cycle refers
to the time period between DOUT/DRDY pulses.
Effective Resolution (ER)—of the ADS1253 in a particular
configuration can be expressed in two different units:
bits rms (referenced to output) and µVrms (referenced to
input). Computed directly from the converter’s output data,
each is a statistical calculation based on a given number of
results. Noise occurs randomly; the rms value represents a
statistical measure that is one standard deviation. The ER in
bits can be computed as follows:
ER in bits rms =
20 log
2
•
•






V
Vrms noise
REF
602.
The 2 • V
REF
figure in each calculation represents the full-
scale range of the ADS1253. This means that both units are
absolute expressions of resolution—the performance in dif-
ferent configurations can be directly compared, regardless of
the units.
f
MOD
—frequency of the modulator and the frequency the
input is sampled.
f
CLK Frequency
MOD
=
6
f
DATA
—Data output rate.
f
f
CLK Frequency
DATA
MOD
==
64 384
Noise Reduction—for random noise, the ER can be im-
proved with averaging. The result is the reduction in noise by
the factor √N
, where N is the number of averages, as shown
in Table V. This can be used to achieve true 24-bit perfor-
mance at a lower data rate. To achieve 24 bits of resolution,
more than 24 bits must be accumulated. A 36-bit accumula-
tor is required to achieve an ER of 24 bits. The following uses
V
REF
= 4.096V, with the ADS1253 outputting data at 20kHz,
a 4096 point average will take 204.8ms. The benefits of
averaging will be degraded if the input signal drifts during that
200ms.
N NOISE ER ER
(Number REDUCTION IN IN
of Averages) FACTOR µVrms BITS rms
1 1 14.6µV 19.1
2 1.414 10.3µV 19.6
427.3µV 20.1
8 2.82 5.16µV 20.6
16 4 3.65µV 21.1
32 5.66 2.58µV 21.6
64 8 1.83µV 22.1
128 11.3 1.29µV 22.6
256 16 0.91µV 23.1
512 22.6 0.65µV 23.6
1024 32 0.46µV 24.1
2048 45.25 0.32µV 24.6
4096 64 0.23µV 25.1
TABLE V. Averaging.