Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External SSOP 16

24-Bit, 20kHz, Low-Power

ANALOG-TO-DIGITAL CONVERTER

FEATURES

● 24 BITS—NO MISSING CODES

● 19 BITS EFFECTIVE RESOLUTION UP TO

20kHz DATA RATE

● LOW NOISE: 1.8ppm

● FOUR DIFFERENTIAL INPUTS

● INL: 15ppm (max)

● EXTERNAL REFERENCE (0.5V to 5V)

● POWER-DOWN MODE

● SYNC MODE

● LOW POWER: 8mW at 20kHz

5mW at 10kHz

DESCRIPTION

The ADS1253 is a precision, wide dynamic range, delta-

sigma, Analog-to-Digital (A/D) converter with 24-bit resolu-

tion operating from a single +5V supply. The delta-sigma

architecture is used for wide dynamic range and 24 bits of no

missing code performance. An effective resolution of 19 bits

(1.8ppm of rms noise) is achieved for conversion rates up to

20kHz.

The ADS1253 is designed for high-resolution measurement

applications in cardiac diagnostics, smart transmitters, indus-

trial process control, weigh scales, chromatography, and

portable instrumentation. The converter includes a flexible,

2-wire synchronous serial interface for low-cost isolation.

The ADS1253 is a 4-channel converter and is offered in an

SSOP-16 package.

APPLICATIONS

● CARDIAC DIAGNOSTICS

● DIRECT THERMOCOUPLE INTERFACES

● BLOOD ANALYSIS

● INFRARED PYROMETERS

● LIQUID/GAS CHROMATOGRAPHY

● PRECISION PROCESS CONTROL

ADS1253

SBAS199B – MAY 2001 – REVISED SEPTEMBER 2007

www.ti.com

ADS1253

4th-Order

∆Σ

Modulator

Digital

Filter

Serial

Interface

Control

CLK

REF

SCLK

DOUT/DRDY

GND

ADS1253

MUX

CH1+

CH1–

CH2+

CH2–

CH3+

CH3–

CH4+

CH4–

CHSEL0

CHSEL1

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

Summary of content (22 pages)

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ADS1253 ADS 125 3 SBAS199B – MAY 2001 – REVISED SEPTEMBER 2007 24-Bit, 20kHz, Low-Power ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● 24 BITS—NO MISSING CODES ● 19 BITS EFFECTIVE RESOLUTION UP TO 20kHz DATA RATE ● LOW NOISE: 1.8ppm ● FOUR DIFFERENTIAL INPUTS ● INL: 15ppm (max) ● EXTERNAL REFERENCE (0.
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ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) Analog Input: Current (Momentary) .............................................. ±100mA (Continuous) ............................................... ±10mA Voltage ................................... GND – 0.3V to VDD + 0.3V VDD to GND ............................................................................ –0.3V to 6V VREF Voltage to GND ............................................... –0.3V to VDD + 0.3V Digital Input Voltage to GND ......
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ELECTRICAL CHARACTERISTICS (Cont.) All specifications at TMIN to TMAX, VDD = +5V, CLK = 8MHz, and VREF = 4.096V, unless otherwise specified. ADS1253E PARAMETER CONDITIONS DIGITAL INPUT/OUTPUT Logic Family Logic Level: VIH VIL VOH VOL Input (SCLK, CLK, CHSEL0, CHSEL1) Hysteresis Data Format MIN TYP MAX UNITS +VDD + 0.3 +0.8 V V V V V CMOS +4.0 –0.3 +4.5 IOH = –500µA IOL = 500µA 0.4 0.
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TYPICAL CHARACTERISTICS At TA = +25°C, VDD = +5V, CLK = 8MHz, and VREF = 4.096V, unless otherwise specified. EFFECTIVE RESOLUTION vs DATA OUTPUT RATE RMS NOISE vs DATA OUTPUT RATE 2.0 20.0 Effective Resolution (Bits) RMS Noise (ppm of FS) 19.8 1.8 1.6 1.4 1.2 19.6 19.4 19.2 19.0 18.8 18.6 18.4 18.2 1.0 100 18.0 1k 10k 100k 100 1k Data Output Rate (Hz) 20.0 1.8 19.8 1.6 19.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 19.4 19.2 19.0 18.8 18.6 18.4 18.2 0 –40 18.
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TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VDD = +5V, CLK = 8MHz, and VREF = 4.096V, unless otherwise specified. INTEGRAL NONLINEARITY vs TEMPERATURE 5 1.8 4 INL (ppm of FS) RMS Noise (ppm of FS) RMS NOISE vs INPUT VOLTAGE (VREF = 5.0V) 2.0 1.6 1.4 3 2 1.2 1 1.
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TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VDD = +5V, CLK = 8MHz, and VREF = 4.096V, unless otherwise specified. CMR AT 60Hz vs CLK FREQUENCY CMR vs COMMON-MODE FREQUENCY –60 –70 –65 –75 –70 –80 CMR (dB) CMR at 60Hz (dB) –75 –80 –85 –90 –95 –85 –90 –95 –100 –100 –105 –110 –105 0 1 2 3 4 5 Clock Frequency (MHz) 6 7 8 10 100 1k 10k Common-Mode Signal Frequency (Hz) POWER DISSIPATION vs CLK FREQUENCY 1.64 9 1.62 8 1.
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THEORY OF OPERATION INPUT MULTIPLEXER The ADS1253 is a precision, high-dynamic range, 24-bit, delta-sigma, A/D converter capable of achieving very highresolution digital results at high data rates. The analog-input signal is sampled at a rate determined by the frequency of the system clock (CLK). The sampled analog input is modulated by the delta-sigma A/D modulator, which is followed by a digital filter.
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DELTA-SIGMA MODULATOR REFERENCE INPUT The ADS1253 operates from a nominal system clock frequency of 8MHz. The modulator frequency is fixed in relation to the system clock frequency. The system clock frequency is divided by 6 to derive the modulator frequency. Therefore, with a system clock frequency of 8MHz, the modulator frequency is 1.333MHz. Furthermore, the oversampling ratio of the modulator is fixed in relation to the modulator frequency.
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frequency must be 19.200kHz, and this sets the data-output rate to 50Hz (see Table I and Figure 4). For 60Hz rejection, the system CLK frequency must be 23.040kHz, and this sets the data-output rate to 60Hz (see Table I and Figure 5). If both 50Hz and 60Hz rejection is required, then the system CLK must be 3.840kHz; this sets the data-output rate to 10Hz and rejects both 50Hz and 60Hz (see Table I and Figure 6). There is an additional benefit in using a lower data-output rate.
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DIGITAL FILTER RESPONSE 0 –20 –20 –40 –40 –60 –60 –80 –80 Gain (dB) Gain (dB) NORMALIZED DIGITAL FILTER RESPONSE 0 –100 –120 –100 –120 –140 –140 –160 –160 –180 –180 –200 –200 0 1 2 3 4 5 6 7 8 9 10 0 50 100 Frequency (Hz) FIGURE 3. Normalized Digital Filter Response.
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DIGITAL FILTER RESPONSE 0 –20 –20 –40 –40 –60 –60 –80 Gain (dB) Gain (dB) DIGITAL FILTER RESPONSE 0 –100 –120 –80 –100 –120 –140 –140 –160 –160 –180 –180 –200 –200 55 56 57 58 59 60 61 62 63 64 55 65 56 57 58 59 60 61 62 63 64 65 Frequency (Hz) Frequency (Hz) FIGURE 9. Expanded Digital Filter Response (60Hz with a 60Hz data output rate). FIGURE 10. Expanded Digital Filter Response (60Hz with a 10Hz data output rate).
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POWER-DOWN MODE SERIAL INTERFACE The normal state of SCLK is LOW; however, by holding SCLK HIGH, the ADS1253 will enter power-down mode. This is accomplished by holding SCLK HIGH for at least 20 consecutive DOUT/DRDY periods (see Figure 14). After the ADS1253 circuitry detects that SCLK has been held HIGH for four consecutive DOUT/DRDY cycles, the DOUT/DRDY pin pulses LOW for one CLK cycle and then is held HIGH, and the modulator is held in a reset state.
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ADS1253 SBAS199B www.ti.com 13 t4 t1 t10 t2 t3 tDRDY t10 t2 t3 FIGURE 15. Power-Down Mode. DOUT/DRDY SCLK CLK tDRDY FIGURE 14. Synchronization Mode. DOUT/DRDY SCLK CLK FIGURE 13. DOUT/DRDY Timing.
PAGE 14
SYSTEM CONSIDERATIONS ISOLATION The serial interface of the ADS1253 provides for simple isolation methods. The CLK signal can be local to the ADS1253, which then only requires two signals (SCLK and DOUT/DRDY) to be used for isolated data acquisition. The channel select signals (CHS0, CHS1) also need to be isolated unless a counter is used to auto multiplex the channels. The recommendations for power supplies and grounding will change depending on the requirements and specific design of the overall system.
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is at 0V and which is at 4.096V. The digital-output result, however, is quite different. The analog-input differential voltage is given by the following equation: +VIN – (–VIN) A positive digital output is produced whenever the analoginput differential voltage is positive, whereas a negative digital output is produced whenever the differential is negative. For example, a positive full-scale output is produced when the converter is configured with a 4.096V reference, and the analog-input differential is 4.
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Revision History DATE REVISION PAGE SECTION DESCRIPTION 9/07 B 12 Table II Changed t11 from 1 • CLK to 3 • CLK. 6/06 A 11 DOUT/DRDY Text changes to DOUT/DRDY section. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 16 ADS1253 www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS1253E/2K5 Package Package Pins Type Drawing SSOP DBQ 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.4 B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1253E/2K5 SSOP DBQ 16 2500 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.