Datasheet

ADS1252
7
SBAS127D
www.ti.com
THEORY OF OPERATION
The ADS1252 is a precision, high-dynamic range, 24-bit, delta-
sigma, A/D converter capable of achieving very high-resolution
digital results at high data rates. The analog-input signal
is sampled at a rate determined by the frequency of the system
clock (CLK). The sampled analog input is modulated by
the delta-sigma A/D modulator, which is followed by a digital
filter. A Sinc
5
digital low-pass filter processes the output of
the delta-sigma modulator and writes the result into the data-
output register. The DOUT/
DRDY pin is pulled LOW, indicating
that new data is available to be read by the external
microcontroller/microprocessor. As shown in the block dia-
gram, the main functional blocks of the ADS1252 are the
4th-order delta-sigma modulator, a digital filter, control logic,
and a serial interface. Each of these functional blocks is
described below.
ANALOG INPUT
The ADS1252 contains a fully differential analog input. In
order to provide low system noise, common-mode rejection
of 100dB, and excellent power-supply rejection, the design
topology is based on a fully differential switched-capacitor
architecture. The bipolar input voltage range is from –4.096
to +4.096V, when the reference input voltage equals +4.096V;
the bipolar range is with respect to –V
IN
, and not with respect
to GND.
With regard to the analog input signal, the overall analog
performance of the device is affected by three items. First,
the input impedance can affect accuracy; therefore, if the
source impedance of the input signal is significant, or if there
is passive filtering prior to the ADS1252, a significant portion
of the signal can be lost across this external impedance. The
magnitude of the effect is dependent on the desired system
performance. See application note
Understanding the
ADS1251, ADS1253, and ADS1254 Input Circuitry
(SBAA086), available for download from TI’s web site,
www.ti.com.
Second, the current into or out of the analog inputs must be
limited. Under no conditions should the current into or out of
the analog inputs exceed 10mA.
Third, to prevent aliasing of the input signal, the bandwidth of
the analog input signal must be band limited; the bandwidth
is a function of the system clock frequency. With a system
clock frequency of 16MHz, the data-output rate is 41.667kHz
with a –3dB frequency of 9kHz, where the –3dB frequency
scales with the system clock frequency.
To ensure the best linearity of the ADS1252, a fully differen-
tial signal is recommended.
BIPOLAR INPUT
The differential inputs of the ADS1252 are designed to
accept differential signals; however, each analog input volt-
age must stay between –0.3V and V
DD
. With a reference
voltage at less than half of V
DD
, one input can be tied to the
reference voltage, and the other input can range from 0V to
2 • V
REF
. By using a single op amp circuit featuring a single
amplifier and four external resistors, the ADS1252 can be
configured to accept bipolar inputs referenced to ground. The
conventional ±2.5V, ±5V, and ±10V input ranges can be
interfaced to the ADS1252 using the resistor values shown in
Figure 1.
FIGURE 1. Level Shift Circuit for Bipolar Input Ranges.
10kΩ
20kΩ
R
1
OPA2350
OPA2350
+IN
–IN
V
REF
ADS1252
R
2
Bipolar Input
REF
2.5V
BIPOLAR INPUT R 1 R 2
±10V 2.5kΩ 5kΩ
±5V 5kΩ 10kΩ
±2.5V 10kΩ 20kΩ