Datasheet

ADS1252
3
SBAS127D
www.ti.com
ELECTRICAL CHARACTERISTICS
All specifications at T
MIN
to T
MAX
, V
DD
= +5V, CLK = 16MHz, and V
REF
= 4.096V, unless otherwise specified.
ADS1252U
PARAMETER CONDITIONS MIN TYP MAX UNITS
ANALOG INPUT
Full-Scale Input Voltage 0 ±V
REF
V
Absolute Input Voltage +V
IN
or –V
IN
to GND –0.3 V
DD
V
Differential Input Impedance CLK = 3.84kHz 125 MΩ
CLK = 1MHz 480 kΩ
CLK = 16MHz 30 kΩ
Input Capacitance 20 pF
Input Leakage At +25°C550pA
At T
MIN
to T
MAX
1nA
DYNAMIC CHARACTERISTICS
Data Rate 41.7 kHz
Bandwidth –3dB 9 kHz
Serial Clock (SCLK) 16 MHz
System Clock Input (CLK) 16 MHz
ACCURACY
Integral Nonlinearity
(1)
±0.0003 ±0.0015 % of FSR
THD 1kHz Input; 0.1dB below FS 97 dB
Noise 2.5 3.8 ppm of FSR, rms
Resolution 24 Bits
No Missing Codes 24 Bits
Common-Mode Rejection
(2)
at DC 90 100 dB
Gain Error 0.4 1 % of FSR
Offset Error ±100 ±200 ppm of FSR
Gain Sensitivity to V
REF
V
REF
= 4.096V ±0.1V 1:1
Power-Supply Rejection Ratio 60 80 dB
PERFORMANCE OVER TEMPERATURE
Offset Drift 0.07 ppm/°C
Gain Drift CLK = 16MHz 7.5 ppm/°C
CLK = 14MHz 5.2 ppm/°C
CLK = 12MHz 3.9 ppm/°C
CLK < 10MHz 3.4 ppm/°C
VOLTAGE REFERENCE
V
REF
0.5 4.096 V
DD
V
Load Current 220 µA
DIGITAL INPUT/OUTPUT
Logic Family CMOS
Logic Level: V
IH
+4.0 +V
DD
+ 0.3 V
V
IL
–0.3 +0.8 V
V
OH
I
OH
= –500µA +4.5 V
V
OL
I
OL
= 500µA 0.4 V
Input (SCLK, CLK) Hysteresis 0.6 V
Data Format Offset Binary Two’s Complement
POWER-SUPPLY REQUIREMENTS
Operation +4.75 +5 +5.25 V
Quiescent Current V
DD
= +5VDC 8 10 mA
Operating Power 40 50 mW
Power-Down Current 110µA
TEMPERATURE RANGE
Operating –40 +85 °C
Storage –60 +100 °C
NOTES: (1) Applies to full-differential signals.
(2) The common-mode rejection test is performed with a 100mV differential input.