Datasheet

ADS1252
15
SBAS127D
www.ti.com
N NOISE ER ER
(NUMBER REDUCTION IN IN
OF AVERAGES) FACTOR µVrms BITS rms
1 1 31.3µV18
2 1.414 22.1µV 18.5
4 2 15.6µV19
8 2.82 11.1µV 19.5
16 4 7.82µV20
32 5.66 5.53µV 20.5
64 8 3.91µV21
128 11.3 2.77µV 21.5
256 16 1.96µV22
512 22.6 1.38µV 22.5
1024 32 978nV 23
2048 45.25 692nV 23.5
4096 64 489nV 24
TABLE IV. Averaging.
result, however, is quite different. The analog-input differen-
tial voltage is given by the following equation:
+V
IN
– (–V
IN
)
A positive digital output is produced whenever the
analog-input differential voltage is positive, whereas negative
digital output is produced whenever the differential is nega-
tive. For example, a positive full-scale output is produced
when the converter is configured with a 4.096V reference,
and the analog-input differential is 4.096V, the negative full-
scale output is produced when the differential voltage is
–4.096V. In each case, the actual input voltages must remain
within the –0.3V to +V
DD
range.
Actual Analog-Input Voltage—the voltage at any one ana-
log input relative to GND.
Full-Scale Range (FSR)—as with most A/D converters, the
full-scale range of the ADS1252 is defined as the input which
produces the positive full-scale digital output minus the input
which produces the negative full-scale digital output. For
example, when the converter is configured with a 4.096V
reference, the differential full-scale range is:
[4.096V (positive full-scale) – (–4.096V) (negative full-scale)] = 8.192V
Least Significant Bit (LSB) Weight—this is the theoretical
amount of voltage that the differential voltage at the analog
input has to change in order to observe a change in the
output data of one least significant bit. It is computed as
follows:
LSB Weight
Full ScaleRange
N
=
−
2
where N is the number of bits in the digital output.
Conversion Cycle—as used here, a conversion cycle refers
to the time period between DOUT/ DRDY pulses.
Effective Resolution (ER)—of the ADS1252 in a particular
configuration can be expressed in two different units:
bits rms (referenced to output) and µVrms (referenced to
input). Computed directly from the converter output data,
each is a statistical calculation based on a given number of
results. Noise occurs randomly; the rms value represents a
statistical measure which is one standard deviation. The ER
in bits can be computed as follows:
ER in bits rms =
20 log
2
•
•






V
Vrms noise
REF
602.
The 2 • V
REF
figure in each calculation represents the
full-scale range of the ADS1252, this means that both units
are absolute expressions of resolution—the performance in
different configurations can be directly compared, regardless
of the units.
Noise Reduction—for random noise, the ER can be im-
proved with averaging. The result is the reduction in noise by
the factor √N
, where N is the number of averages, as shown
in Table IV; this can be used to achieve true 24-bit perfor-
mance at a lower data rate. To achieve 24 bits of resolution,
more than 24 bits must be accumulated. A 36-bit accumula-
tor is required to achieve an ER of 24 bits. The following uses
V
REF
= 4.096V, with the ADS1252 outputting data at 40kHz,
a 4096 point average takes 102.4ms. The benefits of averag-
ing is degraded if the input signal drifts during that 100ms.