Datasheet

ADS1252
11
SBAS127D
www.ti.com
DIGITAL FILTER RESPONSE
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200
56 57 58 59 60 61 62 63 64 6555
Frequency (Hz)
Gain (dB)
DIGITAL FILTER RESPONSE
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200
56 57 58 59 60 61 62 63 64 6555
Frequency (Hz)
Gain (dB)
FIGURE 9. Expanded Digital Filter Response (60Hz with a
60Hz Notch).
FIGURE 10. Expanded Digital Filter Response (60Hz with a
10Hz Notch).
to the DOR from MSB to LSB in the time defined by t
1
(see
Figures 11 and 12). The DOUT/
DRDY line then drives the
line LOW for the time defined by t
2
, and then drives the line
HIGH for the time defined by t
3
to indicate that new data is
available to be read. At this point, the function of the DOUT/
DRDY pin changes to DOUT mode, and data is shifted out
on the pin after t
7
. If the MSB is high (because of a negative
result) the DOUT/DRDY
signal will stay HIGH after the end
of time t
3
. The device communicating with the ADS1252 can
provide SCLKs to the ADS1252 after the time defined by t
6
.
The normal mode of reading data from the ADS1252 is for
the device reading the ADS1252 to latch the data on the
rising edge of SCLK (since data is shifted out of the ADS1252
on the falling edge of SCLK). In order to retrieve valid data,
the entire DOR must be read before the DOUT/
DRDY pin
reverts back to
DRDY mode.
If SCLKs are not provided to the ADS1252 during the DOUT
mode, the MSB of the DOR is present on the DOUT/ DRDY
line until the beginning of the time defined by t
4
. If an
incomplete read of the ADS1252 takes place in DOUT mode
(that is, fewer than 24 SCLKs are provided), the state of the
last bit read is present on the DOUT/
DRDY line until the
beginning of the time defined by t
4
. If more than 24 SCLKs
are provided during DOUT mode, the DOUT/
DRDY line
stays LOW until the beginning of the time defined by t
4
.
The internal data pointer for shifting data out on
DOUT/ DRDY is reset on the falling edge of the time defined
by t
1
and t
4
. This ensures that the first bit of data shifted out
of the ADS1252 after
DRDY mode is always the MSB of new
data.
SYNCHRONIZING MULTIPLE CONVERTERS
The normal state of SCLK is LOW; however, by holding SCLK
HIGH, multiple ADS1252s can be synchronized. This is ac-
complished by holding SCLK HIGH for at least four, but less
than 20, consecutive DOUT/
DRDY cycles (see Figure 13).
After the ADS1252 circuitry detects that SCLK has been held
HIGH for four consecutive DOUT/
DRDY cycles, the DOUT/
DRDY pin pulses LOW for 3 CLK cycles and then held HIGH,
and the modulator is held in a reset state. The modulator
is released from reset and synchronization occurs on the
falling edge of SCLK. It is important to note that prior
to synchronization, the DOUT/
DRDY pulse of multiple
ADS1252s in the system can have a difference in timing up
to one
DRDY period. Therefore, to ensure synchronization,
the SCLK must be held HIGH for at least five
DRDY cycles.
The first DOUT/
DRDY pulse after the falling edge of
SCLK occurs at t
14
. Valid data is not present until the sixth
DOUT/
DRDY pulse.