Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External SOIC 8

24-Bit, 40kHz

ANALOG-TO-DIGITAL CONVERTER

FEATURES

● 24 BITS—NO MISSING CODES

● 19 BITS EFFECTIVE RESOLUTION UP TO

40kHz DATA RATE

● LOW NOISE: 2.5ppm

● DIFFERENTIAL INPUTS

● INL: 0.0015% (max)

● EXTERNAL REFERENCE (0.5V to 5V)

● POWER-DOWN MODE

● SYNC MODE

DESCRIPTION

The ADS1252 is a precision, wide dynamic range, delta-

sigma, Analog-to-Digital (A/D) converter with 24-bit resolu-

tion operating from a single +5V supply. The delta-sigma

architecture is used for wide dynamic range and to ensure 24

bits of no missing code performance. An effective resolution

of 19 bits (2.5ppm of rms noise) is achieved for conversion

rates up to 40kHz.

The ADS1252 is designed for high-resolution measurement

applications in cardiac diagnostics, smart transmitters, indus-

trial process control, weight scales, chromatography, and

portable instrumentation. The converter includes a flexible,

2-wire synchronous serial interface for low-cost isolation.

The ADS1252 is a single-channel converter and is offered in

an SO-8 package.

APPLICATIONS

● CARDIAC DIAGNOSTICS

● DIRECT THERMOCOUPLE INTERFACES

● BLOOD ANALYSIS

● INFRARED PYROMETERS

● LIQUID/GAS CHROMATOGRAPHY

● PRECISION PROCESS CONTROL

ADS1252

SBAS127D – SEPTEMBER 2000 – REVISED JUNE 2006

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

4th-Order

∆Σ

Modulator

Digital

Filter

Serial

Interface

Control

CLK

REF

SCLK

DOUT/DRDY

GND

–V

ADS1252

All trademarks are the property of their respective owners.

Summary of content (21 pages)

PAGE 1
ADS1252 ADS 125 2 SBAS127D – SEPTEMBER 2000 – REVISED JUNE 2006 24-Bit, 40kHz ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● 24 BITS—NO MISSING CODES ● 19 BITS EFFECTIVE RESOLUTION UP TO 40kHz DATA RATE ● LOW NOISE: 2.5ppm ● DIFFERENTIAL INPUTS ● INL: 0.0015% (max) ● EXTERNAL REFERENCE (0.5V to 5V) ● POWER-DOWN MODE ● SYNC MODE The ADS1252 is a precision, wide dynamic range, deltasigma, Analog-to-Digital (A/D) converter with 24-bit resolution operating from a single +5V supply.
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ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) Analog Input: Current ............................................... ±100mA, Momentary ±10mA, Continuous Voltage .................................... GND – 0.3V to VDD + 0.3V VDD to GND ............................................................................ –0.3V to 6V VREF Voltage to GND ............................................... –0.3V to VDD + 0.3V Digital Input Voltage to GND ................................... –0.3V to VDD + 0.
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ELECTRICAL CHARACTERISTICS All specifications at TMIN to TMAX, VDD = +5V, CLK = 16MHz, and VREF = 4.096V, unless otherwise specified. ADS1252U PARAMETER ANALOG INPUT Full-Scale Input Voltage Absolute Input Voltage Differential Input Impedance Input Capacitance Input Leakage CONDITIONS +VIN or –VIN to GND CLK = 3.84kHz CLK = 1MHz CLK = 16MHz PERFORMANCE OVER TEMPERATURE Offset Drift Gain Drift POWER-SUPPLY REQUIREMENTS Operation Quiescent Current Operating Power Power-Down Current 0 –0.
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TYPICAL CHARACTERISTICS At TA = +25°C, VDD = +5V, CLK = 16MHz, and VREF = 4.096V, unless otherwise specified. EFFECTIVE RESOLUTION vs DATA OUTPUT RATE RMS NOISE vs DATA OUTPUT RATE 19.50 3.0 Effective Resolution (bits) RMS Noise (ppm of FS) 2.5 2.0 1.5 1.0 19.25 19.00 18.75 0.5 18.5 0 100 1k 10k 100 100k 1k 10k 100k Data Output Rate (Hz) Data Output Rate (Hz) RMS NOISE vs TEMPERATURE EFFECTIVE RESOLUTION vs TEMPERATURE 3.0 19.0 18.
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TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VDD = +5V, CLK = 16MHz, and VREF = 4.096V, unless otherwise specified. RMS NOISE vs INPUT VOLTAGE EFFECTIVE RESOLUTION vs VREF 3.0 19.00 Effective Resolution (Bits) RMS Noise (ppm of FS) 2.5 2.0 1.5 1.0 0.5 0 18.50 18.00 17.50 17.00 16.50 –5 –4 –3 –2 –1 0 1 2 3 4 5 0 1 2 3 Differential Input Voltage (V) 4 5 6 VREF (V) INTEGRAL NON-LINEARITY vs DATA OUTPUT RATE INTEGRAL NON-LINEARITY vs TEMPERATURE 4 4.0 3.
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TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VDD = +5V, CLK = 16MHz, and VREF = 4.096V, unless otherwise specified. POWER-SUPPLY REJECTION RATIO vs CLK FREQUENCY COMMON-MODE REJECTION RATIO vs CLK FREQUENCY 100 110 95 105 85 CMRR (dB) PSRR (dB) 90 80 75 100 95 90 70 85 65 60 80 0 5 10 15 0 20 5 CURRENT vs TEMPERATURE 15 20 POWER DISSIPATION vs CLOCK FREQUENCY 9.5 45 9.0 40 8.5 35 Power Dissipation (mW) Supply Current (mA) 10 CLK Frequency (MHz) CLK Frequency (MHz) 8.
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THEORY OF OPERATION The ADS1252 is a precision, high-dynamic range, 24-bit, deltasigma, A/D converter capable of achieving very high-resolution digital results at high data rates. The analog-input signal is sampled at a rate determined by the frequency of the system clock (CLK). The sampled analog input is modulated by the delta-sigma A/D modulator, which is followed by a digital filter.
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DELTA-SIGMA MODULATOR REFERENCE INPUT The ADS1252 operates from a nominal system clock frequency of 16MHz which is fixed in relation to the system clock frequency that is divided by 6 to derive the modulator frequency; therefore, with a system clock frequency of 16MHz, the modulator frequency is 2.667MHz. Furthermore, the oversampling ratio of the modulator is fixed in relation to the modulator frequency. The oversampling ratio of the modulator is 64, and with the modulator frequency running at 2.
PAGE 9
For example, if the rejection of power-line frequencies is desired, then the data-output rate can simply be set to the power-line frequency. For 50Hz rejection, the system CLK frequency must be 19.200kHz, and this will set the dataoutput rate to 50Hz (see Table I and Figure 4). For 60Hz rejection, the system CLK frequency must be 20.040kHz, and this will set the data-output rate to 60Hz (see Table I and Figure 5). If both 50Hz and 60Hz rejection is required, then the system CLK must be 3.
PAGE 10
DIGITAL FILTER RESPONSE 0 –20 –20 –40 –40 –60 –60 –80 Gain (dB) Gain (dB) NORMALIZED DIGITAL FILTER RESPONSE 0 –100 –120 –80 –100 –120 –140 –140 –160 –160 –180 –180 –200 –200 0 1 2 3 4 5 6 7 8 9 10 0 50 100 Frequency (Hz) FIGURE 3. Normalized Digital Filter Response. –20 –20 –40 –40 –60 –60 –80 –100 –120 –80 –120 –140 –160 –160 –180 –180 –200 150 200 250 –200 300 0 10 20 30 Frequency (Hz) 50 60 70 80 90 100 FIGURE 6.
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DIGITAL FILTER RESPONSE 0 –20 –40 Gain (dB) –60 –80 –100 –120 –140 –160 –180 –200 55 56 57 58 59 60 61 62 63 64 65 Frequency (Hz) FIGURE 9. Expanded Digital Filter Response (60Hz with a 60Hz Notch). DIGITAL FILTER RESPONSE 0 –20 –40 If SCLKs are not provided to the ADS1252 during the DOUT mode, the MSB of the DOR is present on the DOUT/DRDY line until the beginning of the time defined by t4.
PAGE 12
POWER-DOWN MODE SERIAL INTERFACE The normal state of SCLK is LOW; however, by holding SCLK HIGH, the ADS1252 enters power-down mode. This is accomplished by holding SCLK HIGH for at least 20 consecutive DOUT/DRDY periods (see Figure 14). After the ADS1252 circuitry detects that SCLK is held HIGH for four consecutive DOUT/DRDY cycles, the DOUT/DRDY pin pulses LOW for three CLK cycles, then held HIGH, and the modulator will be held in a reset state.
PAGE 13
ADS1252 SBAS127D www.ti.com 13 t4 t1 t10 t2 t3 tDRDY t10 t2 t3 FIGURE 14. Power-Down Mode. DOUT/DRDY SCLK CLK tDRDY FIGURE 13. Synchronization Mode. DOUT/DRDY SCLK CLK FIGURE 12. DOUT/DRDY Timing.
PAGE 14
ISOLATION The serial interface of the ADS1252 provides for simple isolation methods. The CLK signal can be local to the ADS1252, which then only requires two signals (SCLK and DOUT/DRDY) to be used for isolated data acquisition. LAYOUT POWER SUPPLY The power supply should be well regulated and low noise. For designs requiring very high resolution from the ADS1252, power-supply rejection will be a concern. Avoid running digital lines under the device because they can couple noise onto the die.
PAGE 15
result, however, is quite different. The analog-input differential voltage is given by the following equation: +VIN – (–VIN) A positive digital output is produced whenever the analog-input differential voltage is positive, whereas negative digital output is produced whenever the differential is negative. For example, a positive full-scale output is produced when the converter is configured with a 4.096V reference, and the analog-input differential is 4.
PAGE 16
Revision History DATE REVISION PAGE SECTION 6/06 D 11 DOUT/DRDY DESCRIPTION Text changes to DOUT/DRDY section. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 16 ADS1252 www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.