Datasheet

ADS1251
8
SBAS184D
www.ti.com
DELTA-SIGMA MODULATOR
The ADS1251 operates from a nominal system clock fre-
quency of 8MHz. The modulator frequency is fixed in relation
to the system clock frequency. The system clock frequency
is divided by 6 to derive the modulator frequency (f
MOD
).
Therefore, with a system clock frequency of 8MHz, the
modulator frequency is 1.333MHz. Furthermore, the
oversampling ratio of the modulator is fixed in relation to the
modulator frequency. The oversampling ratio of the modula-
tor is 64, and with the modulator frequency running at
1.333MHz, the data rate is 20.8kHz. Using a slower system
clock frequency will result in a lower data output rate, as
shown in Table I.
REFERENCE INPUT
The reference input takes an average current of 32µA with a
8MHz system clock. This current will be proportional to the
system clock. A buffered reference is recommended for the
ADS1251. The recommended reference circuit is shown in
Figure 2.
Reference voltages higher than 4.096V will increase the full-
scale range, while the absolute internal circuit noise of the
converter remains the same. This will decrease the noise in
terms of ppm of full-scale, which increases the effective
resolution (see typical characteristic
RMS Noise vs V
REF
Voltage ).
DIGITAL FILTER
The digital filter of the ADS1251, referred to as a Sinc
5
filter,
computes the digital result based on the most recent outputs
from the delta-sigma modulator. At the most basic level, the
digital filter can be thought of as averaging the modulator
results in a weighted form and presenting this average as the
digital output. The digital output rate, or data rate, scales
directly with the system clock frequency. This allows the data
output rate to be changed over a very wide range (five orders
of magnitude) by changing the system clock frequency.
However, it is important to note that the –3dB point of the
filter is 0.2035 times the data output rate, so the data output
rate should allow for sufficient margin to prevent attenuation
of the signal of interest.
As the conversion result is essentially an average, the
data-output rate determines the location of the resulting
notches in the digital filter (see Figure 3). Note that the first
notch is located at the data output rate frequency, and
subsequent notches are located at integer multiples of the
data output rate; this allows for rejection of not only the
fundamental frequency, but also harmonic frequencies. In
this manner, the data output rate can be used to set specific
notch frequencies in the digital filter response.
For example, if the rejection of power-line frequencies is
desired, then the data output rate can simply be set to the
power-line frequency. For 50Hz rejection, the system clock
TABLE I. CLK Rate versus Data Output Rate.
CLK (MHz) DATA OUTPUT RATE (Hz)
8
(1)
20,833
7.372800
(1)
19,200
6.144000
(1)
16,000
6.000000
(1)
15,625
4.915200
(1)
12,800
3.686400
(1)
9600
3.072000
(1)
8000
2.457600
(1)
6400
1.843200
(1)
4800
0.921600 2400
0.460800 1200
0.384000 1000
0.192000 500
0.038400 100
0.023040 60
0.019200 50
0.011520 30
0.009600 25
0.007680 20
0.006400 16.67
0.005760 15
0.004800 12.50
0.003840 10
NOTE: (1) Standard Clock Oscillator.
FIGURE 2. Recommended External Voltage Reference Circuit for Best Low-Noise Operation with the ADS1251.
0.10µF
+5V
10kΩ
10µF
4
3
2
7
6
+
0.10µF
0.1µF
10µF
+
0.1µF
OPA350
0.1µF
+5V
3
1
2
To V
REF
Pin 8 of
the ADS1251
REF3040